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TMS320F28377D-Q1: Signal applied during calibration

Ronald Belt
Prodigy 10 points
Part Number: TMS320F28377D-Q1
Other Parts Discussed in Thread: TMS320F2811

When doing a calibration on the TMS320F28377 while using an external VREF, is it assumed that the calibration signal applied to the ADC input is a maximum signal equal to the external VREF?  With this assumption it appears from the documentation that only an offset correction is obtained.  What would happen if the signal applied to the ADC input is not a maximum signal, but something like 50% to 80% of the maximum signal of VREF?  Would the calibration also produce a gain correction that would cause all signals converted afterward to read higher than normal by the inverse ratio of the calibration signal to the maximum signal?  (I realize that the calibration signal should be a regulated voltage like the VREF voltage, but a circuit I am analyzing has used a non-regulated signal instead).

Related question:  Do the same answers apply to the TMS320F2811 DSP?

  • +1
    TI__Guru* 75360 points

    Ronald,

    Thanks for reaching out to the TI E2E forum.

    I'd like to first clarify some terminology that we use in our reference manuals to make sure we are talking apples to apples(or calibration to calibration as it were!)

    For the F2837x devices there is mention about "factory calibration" and "zero-offset calibration"

    1)Factory Calibration: For each ADC we test and "trim" in our production line such that the ADC will meet the datasheet specifications for things like gain/offset, etc.  We store these values in TI OTP memory and rely on FW(either in the BROM or in user code) to load these values from the OTP to the ADC so that the ADC will be in specification.

    2)Zero-offset Calibration:  While a chip level offset calibration is taken care in the above factory cal; we provide an option to further correct for any potential board level offsets via sampling of the VREFLO pin and re-adjusting the Offset Trim register.  This trim is implemented in the analog domain, so there is no loss in dynamic range nor change in the sampling speed of the ADC(vs something done in the digital domain).

    In your example you mention using a known reference voltage to further calibrate the ADC.  Assuming we have done a zero-offset self calibration and there is no longer any offset(the "b" in a y=mx+b interpretation of the ADC transfer function), the goal here would be to reduce the full scale error or gain error(the "m" in the earlier equation).

    At any rate, to my knowledge we don't actively support changing the ANAREF register values to "re-tune" the ADC dynamically in the analog space.  So we would be looking to calibrate out any gain error post processing it by the C28x(or CLA) to negate the error we see when sampling a known reference voltage.

    In the case you mention in your post, we would actually prefer a voltage that is lower than VREFHI; in case we have positive gain error.  This is because if we sample VREFHI(which is equal to the Full Scale Range of the ADC) and there is positive gain error we will saturate the ADC result and not be able to determine the error. 

    In this case we would calculate the "m" by simply dividing the ADC Result when sampling this reference voltage by the ideal code it should produce if we assume no gain or offset.  Once we have this any subsequent ADC conversion could be divided by this number to get the calibrated version.

    The same would apply for the F2811, this application note helps explain alot of what I mentioned above.

    Keep in mind that the F2811 does not have the dynamic offset correction that is present on the F2837x, so you'll see a 2 point approach on that device to remove offset error manually as well.

    Let me know if you have further questions.

    Best,

    Matthew