TMS320F28069M: SCI Issue: SCI_getRxFifoStatus alway read empty

Hi

I have set up SCI RX FIFO (while TX- FIFO is disabled) with 2 words that trigger interrupt. The interrupt is working fine under FIFO but I keep getting zero counts of SCI_getRxFifoStatus(), which suggests no data received in RX FIFO (while interrupt actually happens). 

Earlier code where FIFO is not used, it runs fine with 115K2 and 57K6 BAUD. There nothing wrong with hardware from the custom board. 

I have read the datasheet and example demo code several times, it seems not to use SCI_getRxFifoStatus to get counts of FIFO fills in demo code.

Attached below code and debug register dump. I'm using hal object to set up FIFO RX interrupts. 

Have I missed something?

#pragma CODE_SECTION(SCI_RX_ISR,"ramfuncs");
uint16_t NoOfData;
interrupt void SCI_RX_ISR(void)
{
    uint16_t success;
    HAL_Obj *obj = (HAL_Obj *)halHandle;
    zUDT_Obj *uobj = (zUDT_Obj *) zUDTHandle;
    SCI_Obj *sci = (SCI_Obj *)obj->sciHandle[0];

    PIE_clearInt(obj->pieHandle,PIE_GroupNumber_9);  // acknowledge interrupt from SCI group so that SCI interrupt
    CPU_disableGlobalInts(obj->cpuHandle);
    //while(SCI_getRxFifoStatus(halHandle->sciHandle[0]) == SCI_FifoStatus_Empty)
    //{};
    //---------------------------------------Read data into buffer.
    NoOfData = ((sci->SCIFFRX) >>8) & 0x000F;
    for (int i=0; i<NoOfData; i++)
    {

void HAL_setupSCI(HAL_Handle handle)
{
    HAL_Obj *obj = (HAL_Obj *) handle;
    SCI_Obj *sci = (SCI_Obj *)obj->sciHandle[0];

    SCI_reset(obj->sciHandle[0]);
    SCI_enableTx(obj->sciHandle[0]);
    SCI_enableRx(obj->sciHandle[0]);        // SCICTL1.RXENA  Bit 0.
    //---------------------------------------Serial Definition
    SCI_setNumStopBits(obj->sciHandle[0], SCI_NumStopBits_One);
    //SCI_setParity(obj->sciHandle[0], SCI_Parity_Odd);
    SCI_disableParity(obj->sciHandle[0]);
    SCI_disableLoopBack(obj->sciHandle[0]);
    //SCI_setBaudRate(obj->sciHandle[0], SCI_BaudRateRVP_57_6_kBaud);         //Reliable use.
    SCI_setBaudRate(obj->sciHandle[0], SCI_BaudRateRVP_115_2_kBaud);      //Not so reliable, Maybe FIFO help
    SCI_setCharLength(obj->sciHandle[0], SCI_CharLength_8_Bits);
    //========================================RX Side Only with FIFO setup. Updated RP:30/Apr/21.
    // This is working FIFO setting from demo code.
    //  SCIFFRX = 0x2022
    //  SCICTL2 = 0x00C2
    //  SCICTL1 = 0x0023
    //----------------sci->SCIFFRX =0x0022;       // Bit 5 and 1
    SCI_setRxFifoIntLevel(obj->sciHandle[0],(SCI_FifoLevel_e)SCI_FifoLevel_2_Words);
    SCI_enableRxFifoInt(obj->sciHandle[0]);
    //----------------sci->SCIFFCT=0x00;          // Autoband off, not needed. Default is 0 anyway.
    sci->SCIFFCT=0x00;
    //----------------sci->SCICTL2 |= SCI_SCICTL2_RX_INT_ENA_BITS;
    SCI_enableRxInt(obj->sciHandle[0]);
    //----------------sci->SCIFFRX |= SCI_SCIFFRX_FIFO_RESET_BITS;
    sci->SCIFFRX |= SCI_SCIFFRX_FIFO_RESET_BITS;
    //SCI_enableRxFifo(obj->sciHandle[0]);          // This set bit 13 of SCIFFRX
    //SCI_resetRxFifo(obj->sciHandle[0]);
    //=========================================TX Side Only, no FIFO since it polling.
    SCI_disableTxWake(obj->sciHandle[0]);
    SCI_disableSleep(obj->sciHandle[0]);
    //SCI_enableTxFifo(obj->sciHandle[0]);
    //SCI_enableTxFifoEnh(obj->sciHandle[0]);
    SCI_disableTxInt(obj->sciHandle[0]);
    //---------------------------------------Misc.
    SCI_setMode(obj->sciHandle[0], SCI_Mode_IdleLine);
    SCI_setPriority(obj->sciHandle[0],SCI_Priority_FreeRun);
    //---------------------------------------Activate SCI
    SCI_enable(obj->sciHandle[0]);
    //---------------------------------------System INT.
    PIE_enableInt(obj->pieHandle,PIE_GroupNumber_9,PIE_InterruptSource_SCIARX);     // enable SCIA RX interrupt in PIE
    SCI_enableRxInt(obj->sciHandle[0]);           // for both FIFO or non-FIFO use.                                    // enable SCIA RX interrupt
    CPU_enableInt(obj->cpuHandle,CPU_IntNumber_9);