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TMS320F280049: Oscillator CPU timer test (SDL LIB) questions

Marc Ferrer
Prodigy 100 points
Part Number: TMS320F280049


Hello expert, 

I am implementing CLK2 (oscillator CPU timer test) safety mechanism using the SDL lib file stl_osc_ct.  I followed hte example provided in C200ware and have some doubts:

-   example uses 13,107,000 cycles at DEVICE_SYSCLK_FREQ. Question is if we need so many counts or this value can be modified ? Due to using so many sysclk cycles, I need to disable watchdog to avoid triggering an interrupt, which I expect to have no side effect, but I would like to know if this can be avoided.

- Do we need to check more clock sources or prescaler options? Example uses system clock as source and prescaler_1, but would it be advisable to repeat test with other clock sources and/or prescaler values?

Many thanks,

Marc

  • +1
    TI__Guru 53925 points

    I don't recall where that number of cycles came from, but yes, you can use a smaller more suitable value. CLK2 in the FSM just says, "Common cause failures can be reduced by using different clock sources and different prescale values for the reference clock and measured clock." I'm not sure trying multiple prescalers is adding much value, but I can see value in trying different clock sources if you have time. I think the independence is the most important thing--like if SYSCLK is running off of the XTAL, have CPU Timer 2 run off of INTOSC2.

    Whitney

  • 0 in reply to Whitney Dewey
    Prodigy 100 points

    Hi Whitney,

    Thanks for the feedback. In my case SYSCLK is running off of the XTAL so I am planning to perform the following:

    1. Perform test at startup with CPU Timer 2 running off of SYSCLK to check its own integrity.

    2. Perform test at startup with CPU Timer 2 running off of INTOSC2 to check integrity between timers.

    Is this strategy correct and aligned with your previous feedback?

    Many thanks,

    Marc

  • 0 in reply to Marc Ferrer
    TI__Guru 53925 points

    Marc, that plan sounds good.

    Whitney