Daisy-chained SPI bus: master and cooperative slaves

Tarik,

I'm not aware of any SW example on the C2000 MCU family of devices for SPI daisy chain.  Do you mean you would daisy chain 15 C2000 MCUs?  This could be done in SW to an extent with some delay in data in to data out.  Most of our newer devices have a DMA that could take care of reading the incoming message and then pushing it right back to the Tx buffer without CPU intervention. 

You may want to post this question to the Processors forum as well to see if this is something they have encountered(although a quick search of the E2E didn't show anything).

I think the key is that the downstream devices have to support this style of SPI, most may lack a CPU to do any decoding of the message, etc.

If you want to share more info on your proposed system or devices I can try to get a bit more granular.

Best,

Matthew

Salut Matthew,

I am using a circuit 20XS4200 HIGH-SIDE SWITCH and, I want a basic driver if it exists, please.

My idea is to use plenty of this circuit in series using SPI communication each MOSI element will connect MISO next element but, the driver must be generic since I will add many of 20XS4200

what is the best strategy for a generic driver for many components of the same circuit (20XS4200)?

I am using the TMS320F280049 MCU. 

Thank you in advance and please guide me if I am in the wrong place,

Tarik,

Looking at the 20XS4200, it has a CS signal.  If you had multiples of these, could they be wired in parallel to each of the downstreams peripherals and use different GPIOs from the F280049 device to control the individual chip selects?

Best,

Matthew