TMS320F280049C: Mixing Burst mode and High prio

Hi Jan,

Yes, the high priority SOCs will convert as soon as the ADC has a free slot, including in the middle of a sequence of burst SOCs.  Since the burst size is 1, you won't really have a burst sequence to interrupt, just a single SOC, but if a high priority SOC is converting and the burst trigger is received, the burst SOC will be delayed until the currently converting SOC completes.  This really doesn't have anything to do with priority, just that the ADC will never drop an in-progress conversion, so you'll always run into this issue with async. trigger sources.

Yes, the way to go (if you are using a single ADC) would be to set the burst mode to trigger two SOCs at a time. The first SOC is always the fast signal and the 2nd one rotates through the various low-speed sampling signals.

e.g.

SOC0 = fast ch 1, SOC1 = slow channel 1

SOC2 = fast ch 1, SOC3 = slow channel 2

SOC4 = fast ch 1, SOC5 = slow channel 3

... etc,

In this case, the slow channels get sampled at 1/8 the speed of the fast channel if you use all the SOCs.  You may also end up filling some slow channel slots with dummy conversions if you have less than 8 slow channels.   

There are also other ways to manage this, such as setting the fast channel and slow channels to be regular SOCs and then triggering them with different speed ePWMs which are synchronous frequency multiples (e.g. 200kHz and 10kHz) but out-of-phase such that the slower trigger occurs after the fast trigger completes.  This assumes that all the slow signals could fit between two 200kHz triggers.  If not, you'd again need to use burst mode for the slower trigger.   

The thing is, that I run into performance Issues. When having two interrupts where each is triggered every 200ks/8bs (kilo samples/burst size)  my performace is at maximum limit. I probably even need to sample 3 Signals with 200 ksp. I could maybe invoke only 1 interrupt and getting the samples only from that particular interrupt.

Or is it possible to configure one dma to get the samples of soc0,2,4,6,...,14?

Hi Jan,

For the 3 signals, are you not already using the 3 ADCs to process these in parallel?  In this case, you still only need one ISR (just pick an ADC to trigger the ISR, but gather all the samples in that ISR).

I think it is probably possible to configure the DMA to get RESULT0, RESULT2, RESULT4...etc.  If you are having trouble with this configuration, you might create a new thread on that topic specifically (it'll then get assigned to the DMA expert).   

I would like to delay one of the high sampled inputs, in order to compensate the delay of the other signals. What is the best way then to delay it and just use one ISR. Using burst mode to delay the input? What I don't like from software design aspect to get all my signals in one ISR, but that is something I probaly cannot prevent. 

Furthermore, I want to do crossing zero detection on one of the 3 signals. Is there an example in the driver ware?

Kind Regards

Jan

I did a little debugging and getting one sample from the result register is taking about 100 Ticks, when getting 28 samples from the result buffers, this allone would take 2800 Ticks. When the interrupt  is triggered arround every 4000 Ticks, there is not a lot of spare time left...  Static inlining is not turend on, therefore the function call every time calling ADC_readResult will cause an overhead, getting it directly from the register will boost my performace. I will do some evaluation on that.

I think I can explain it in words. I want current and voltage to be synchronous. Since they are not measured direclty and differently filtered, I would like trying to shift my measurments a little bit, in order to make them synchronious. The best thing would be, if array_current[i] has a directe relation to array_voltage[i], and they are not shifted anymore. Our opt level is off... Using optimizations make it harder to admission...

Hi Jan,

I still don't fully understand the issue, but I think the ADCs are fast enough together to sample all the signals in one sequence of conversions (assuming close to minimum S+H times): 3.5MSPS x 3 / 28 = 375kHz which is faster than 200kHz.  If the bottleneck is reading the results you could do this over multiple ISRs (and only trigger and read updated results on the "high speed" signals every 200kHz period)? This would ensure the samples are correlated.  I think in this case you'd need a spare ePWMs synchronized to the fast ePWM to trigger to trigger all the slow signals.    

Hello Devin,

lets start with the crossing zero detection: I just quickly checked the example and the crossing zero is bound to a Soc, so if I sample a signal in burst mode with lets say 8 Socs, won't I miss the event then? 

I think I will be able to handle the performance issues with your information, thanks.