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Original question:

TMS320F28034: Does the F28034 eCAN return ACK for out-of-target IDs?

TMS320F28034: LIN regisiter question

Gabriel Wang1
Genius 4795 points
Part Number: TMS320F28034


Dear Expert

I found several problems during online simulation during debugging 28034 LIN (serial port use) these two days.

Question 1: the LinaRegs SCIGCR1 register nothing happened, the program execution, LinaRegs. SCIGCR1. Bit. TXENA procedures and documentation, CCS register no.

Question 2: LinaRegs.SCIFORMAT in CCS is changed and does not match the actual register.

Question 3: Other registers are not the same as the actual configuration.

The above issues have been debugged online in CCS9.0,CCS9.3 and CCS10.3. The problems are the same .

  • 0
    TI__Mastermind 25800 points

    Hi Gabriel,

    What happens if you view the registers within the Memory Browser view of CCS? You can choose the Peripheral option and go to the LIN address to view all of the LIN registers. Is the value there correct? 

    Best Regards,

    Marlyn

  • 0
    Guru 92251 points
    Gabriel Wang1 said:
    I found several problems during online simulation during debugging 28034 LIN (serial port use) these two days

    In CCS/TMS320F28035: LIN_REGS Registers have wrong addr offset in ccs it was found that the ccs/ccs_base/common/targetdb/Modules/C2000/C2000_LIN_Type0_Registers.xml file used by CCS has incorrect offsets for the LIN Type0 registers used in a TMS320F28034. This means the CCS debugger doesn't show the correct register values.

    I have checked a CCS 10.3.0.00007 installation with C2000 Device Support 6.1.0.0 and the problem is still present.

    Not sure if a defect has been raised on the incorrect register definitions used by CCS.

  • 0 in reply to Chester Gillon
    TI__Mastermind 25800 points

    Hi Chester,

    Thank you for sharing. I will work on getting the xml file updated with the correct offsets.

    Best Regards,

    Marlyn

  • 0 in reply to Marlyn Rosales Castaneda20
    TI__Mastermind 25800 points

    Hi Gabriel and Chester,

    The C2000_LIN_Type0_Registers.xml file will be corrected in the next CCS release, v11. 

    In the mean time, I have attached the updated xml file with the correct offsets.

     

    Fullscreen C2000_LIN_Type0_Registers.xml Download 
    <?xml version="1.0" encoding="UTF-8"?>

<!-- Lin Registers -->
<module id="LIN" HW_revision="" XML_version="1" description="LIN Registers">
	<register id="SCIGCR0" acronym="SCIGCR0" offset="0x0" page="1" width="32" description="Global Control Register 0" >
		<bitfield id="RESET" description="LIN Module reset bit" begin="0" end="0" width="1" rwaccess="R/W"/>
	</register>
	<register id="SCIGCR1" acronym="SCIGCR1" offset="0x2" page="1" width="32" description="Global Control Register 1" >
		<bitfield id="COMMODE" description="SCI/LIN communications mode bit" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="TIMINGMODE" description="SCI timing mode bit" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="PARITYENA" description="Parity enable" begin="2" end="2" width="1" rwaccess="R/W"/>
		<bitfield id="PARITY" description="SCI parity odd/even selection" begin="3" end="3" width="1" rwaccess="R/W"/>
		<bitfield id="STOP" description="SCI number of stop bits" begin="4" end="4" width="1" rwaccess="R/W"/>
		<bitfield id="CLK_MASTER" description="LIN Master/Slave selection and SCI clock enable" begin="5" end="5" width="1" rwaccess="R/W"/>
		<bitfield id="LINMODE" description="LIN Mode enable/disable" begin="6" end="6" width="1" rwaccess="R/W"/>
		<bitfield id="SWnRST" description="Software reset" begin="7" end="7" width="1" rwaccess="R/W"/>
		<bitfield id="SLEEP" description="SCI sleep (SCI compatibility  mode)" begin="8" end="8" width="1" rwaccess="R/W"/>
		<bitfield id="ADAPT" description="Automatic baudrate adjustment control (LIN mode)" begin="9" end="9" width="1" rwaccess="R/W"/>
		<bitfield id="MBUFMODE" description="Multi-buffer mode" begin="10" end="10" width="1" rwaccess="R/W"/>
		<bitfield id="CTYPE" description="Checksum type (LIN mode)" begin="11" end="11" width="1" rwaccess="R/W"/>
		<bitfield id="HGENCTRL" description="Mask filtering comparison control (LIN mode)" begin="12" end="12" width="1" rwaccess="R/W"/>
		<bitfield id="STOPEXTFRAME" description="Stop extended frame communication  (LIN mode)" begin="13" end="13" width="1" rwaccess="R/W"/>
		<bitfield id="LOOPBACK" description="Digital loopback mode" begin="16" end="16" width="1" rwaccess="R/W"/>
		<bitfield id="CONT" description="Continue on suspend" begin="17" end="17" width="1" rwaccess="R/W"/>
		<bitfield id="RXENA" description="SCI mode receiver enable" begin="24" end="24" width="1" rwaccess="R/W"/>
	</register>	
	<register id="SCIGCR2" acronym="SCIGCR2" offset="0x4" page="1" width="32" description="Global Control Register 2" >
		<bitfield id="POWERDOWN" description="Low-power mode PowerDown bit" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="GENWU" description="Genereate Wakeup" begin="8" end="8" width="1" rwaccess="R/W"/>
		<bitfield id="SC" description="Send Checksum (LIN mode)" begin="16" end="16" width="1" rwaccess="R/W"/>
		<bitfield id="CC" description="Compare Checksum (LIN mode))" begin="17" end="17" width="1" rwaccess="R/W"/>
	</register>
	<register id="SCISETINT" acronym="SCISETINT" offset="0x6" page="1" width="32" description="Interrupt Enable Register" >
		<bitfield id="SETBRKDTINT" description="Set Break-detect Interrupt (SCI compatible mode)" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="SETWAKEUPINT" description="Set Wake-up Interrupt" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="SETTIMEOUTINT" description="Set Timeout Interrupt (LIN Only)" begin="4" end="4" width="1" rwaccess="R/W"/>
		<bitfield id="SETTOAWUSINT" description="Set Timeout After Wakeup Signal Interrupt" begin="6" end="6" width="1" rwaccess="R/W"/>
		<bitfield id="SETTOA3WUSINT" description="Set Timeout After 3 Wakeup Signals Interrupt (LIN only)" begin="7" end="7" width="1" rwaccess="R/W"/>
		<bitfield id="SETTXINT" description="Set Transmitter Interrupt" begin="8" end="8" width="1" rwaccess="R/W"/>
		<bitfield id="SETRXINT" description="Receiver Interrupt Enable" begin="9" end="9" width="1" rwaccess="R/W"/>
		<bitfield id="SETIDINT" description="Set Identifier Interrupt (LIN only)" begin="13" end="13" width="1" rwaccess="R/W"/>
		<bitfield id="SETPEINT" description="Set Parity Interrupt" begin="24" end="24" width="1" rwaccess="R/W"/>
		<bitfield id="SETOEINT" description="Set Overrun-Error Interrupt" begin="25" end="25" width="1" rwaccess="R/W"/>
		<bitfield id="SETFEINT" description="Set Framing-Error Interrupt" begin="26" end="26" width="1" rwaccess="R/W"/>
		<bitfield id="SETNREINT" description="Set No-Response-Error Interrupt (LIN only)" begin="27" end="27" width="1" rwaccess="R/W"/>
		<bitfield id="SETISFEINT" description="Set Inconsistent-Synch-Field-Error Interrupt (LIN only)" begin="28" end="28" width="1" rwaccess="R/W"/>
		<bitfield id="SETCEINT" description="Set Checksum-error Interrupt (LIN only)" begin="29" end="29" width="1" rwaccess="R/W"/>
		<bitfield id="SETPBEINT" description="Set Physical Bus Error Interrupt (LIN only)" begin="30" end="30" width="1" rwaccess="R/W"/>
		<bitfield id="SETBEINT" description="Set Bit Error Interrupt (LIN only)" begin="31" end="31" width="1" rwaccess="R/W"/>			
	</register>
	<register id="SCICLEARINT" acronym="SCICLEARINT" offset="0x8" page="1" width="32" description="Interrupt Disable Register" >
		<bitfield id="CLRBRKDTINT" description="Clear Break-detect Interrupt (SCI compatible mode)" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="CLRWAKEUPINT" description="Clear Wake-up Interrupt" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTIMEOUTINT" description="Clear Timeout Interrupt (LIN only)" begin="4" end="4" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTOAWUSINT" description="Clear Timeout After Wakeup Signal Interrupt (LIN only)" begin="6" end="6" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTOA3WUSINT" description="Clear Timeout After 3 Wakeup Signals Interrupt (LIN only)" begin="7" end="7" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTXINT" description="Clear Transmitter Interrupt" begin="8" end="8" width="1" rwaccess="R/W"/>
		<bitfield id="CLRRXINT" description="Clear Receiver Interrupt" begin="9" end="9" width="1" rwaccess="R/W"/>
		<bitfield id="CLRDINT" description="Clear Identifier Interrupt (LIN only)" begin="13" end="13" width="1" rwaccess="R/W"/>
		<bitfield id="CLRPEINT" description="Clear Parity Interrupt" begin="24" end="24" width="1" rwaccess="R/W"/>
		<bitfield id="CLROEINT" description="Clear Overrun-Error Interrupt" begin="25" end="25" width="1" rwaccess="R/W"/>
		<bitfield id="CLRFEINT" description="Clear Framing-Error Interrupt" begin="26" end="26" width="1" rwaccess="R/W"/>
		<bitfield id="CLRNREINT" description="Clear No-Response-Error Interrupt (LIN only)" begin="27" end="27" width="1" rwaccess="R/W"/>
		<bitfield id="CLRISFEINT" description="Clear Inconsistent-Synch-Field-Error Interrupt (LIN only)" begin="28" end="28" width="1" rwaccess="R/W"/>
		<bitfield id="CLRCEINT" description="Clear Checksum-error Interrupt (LIN only)" begin="29" end="29" width="1" rwaccess="R/W"/>
		<bitfield id="CLRPBEINT" description="Clear Physical Bus Error Interrupt (LIN only)" begin="30" end="30" width="1" rwaccess="R/W"/>
		<bitfield id="CLRNREINT" description="Clear Bit Error Interrupt (LIN only)" begin="31" end="31" width="1" rwaccess="R/W"/>
	</register>
	<register id="SCISETINTLVL" acronym="SCISETINTLVL" offset="0xA" page="1" width="32" description="Set Interrupt Level Register" >
		<bitfield id="SETBRKDTINTLVL" description="Set Break-detect Interrupt Level (SCI Compatible Mode)" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="SETWAKEUPINTLVL" description="Set Wake-up Interrupt Level" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="SETTIMEOUTINTLVL" description="Set Timeout Interrupt Level (LIN only)" begin="4" end="4" width="1" rwaccess="R/W"/>
		<bitfield id="SETTOAWUSINTLVL" description="Set Timeout After Wakeup Signal Interrupt Level (LIN only)" begin="6" end="6" width="1" rwaccess="R/W"/>
		<bitfield id="SETTOA3WUSINTLVL" description="Set Timeout After 3 Wakeup Signals" begin="7" end="7" width="1" rwaccess="R/W"/>
		<bitfield id="SETTXINTLVL" description="Set Transmitter Interrupt Level" begin="8" end="8" width="1" rwaccess="R/W"/>
		<bitfield id="SETRXINTOVO" description="Receiver Interrupt Enable Level" begin="9" end="9" width="1" rwaccess="R/W"/>
		<bitfield id="SETIDINTLVL" description="Set Identifier Interrupt Level (LIN only)" begin="13" end="13" width="1" rwaccess="R/W"/>
		<bitfield id="SETPEINTLVL" description="Set Parity Interrupt Level" begin="24" end="24" width="1" rwaccess="R/W"/>
		<bitfield id="SETOEINTLVL" description="Set Overrun-Error Interrupt Level" begin="25" end="25" width="1" rwaccess="R/W"/>
		<bitfield id="SETFEINTLVL" description="Set Framing-Error Interrupt Level" begin="26" end="26" width="1" rwaccess="R/W"/>
		<bitfield id="SETNREINTLVL" description="Set No-Response-Error Interrupt Level (LIN only)" begin="27" end="27" width="1" rwaccess="R/W"/>
		<bitfield id="SETISFEINTLVL" description="Set Inconsistent-Synch-Field-Error Interrupt Level" begin="28" end="28" width="1" rwaccess="R/W"/>
		<bitfield id="SETCEINTLVL" description="Set Checksum-error Interrupt Level (LIN only)" begin="29" end="29" width="1" rwaccess="R/W"/>
		<bitfield id="SETPBEINTLVL" description="Set Physical Bus Error Interrupt Level (LIN only)" begin="30" end="30" width="1" rwaccess="R/W"/>
		<bitfield id="SETBEINTLVL" description="Set Bit Error Interrupt Level (LIN only)" begin="31" end="31" width="1" rwaccess="R/W"/>
	</register>
	<register id="SCICLEARINTLVL" acronym="SCICLEARINTLVL" offset="0xC" page="1" width="32" description="Clear Interrupt Level Register" >
		<bitfield id="CLRBRKDTINTLVL" description="Clear Break-detect Interrupt Level (SCI Compatible Mode)" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="CLRWAKEUPINTLVL" description="Clear Wake-up Interrupt Level" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTIMEOUTINTLVL" description="Clear Timeout Interrupt Level (LIN only)" begin="4" end="4" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTOAWUSINTLVL" description="Clear Timeout After Wakeup Signal Interrupt Level (LIN only)" begin="6" end="6" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTOA3WUSINTLVL" description="Clear Timeout After 3 Wakeup Signals" begin="7" end="7" width="1" rwaccess="R/W"/>
		<bitfield id="CLRTXINTLVL" description="Clear Transmitter Interrupt Level" begin="8" end="8" width="1" rwaccess="R/W"/>
		<bitfield id="CLRRXINTOVO" description="Clear Receiver Interrupt Enable Level" begin="9" end="9" width="1" rwaccess="R/W"/>
		<bitfield id="CLRIDINTLVL" description="Clear Identifier Interrupt Level (LIN only)" begin="13" end="13" width="1" rwaccess="R/W"/>
		<bitfield id="CLRPEINTLVL" description="Clear Parity Interrupt Level" begin="24" end="24" width="1" rwaccess="R/W"/>
		<bitfield id="CLROEINTLVL" description="Clear Overrun-Error Interrupt Level" begin="25" end="25" width="1" rwaccess="R/W"/>
		<bitfield id="CLRFEINTLVL" description="Clear Framing-Error Interrupt Level" begin="26" end="26" width="1" rwaccess="R/W"/>
		<bitfield id="CLRNREINTLVL" description="Clear No-Response-Error Interrupt Level (LIN only)" begin="27" end="27" width="1" rwaccess="R/W"/>
		<bitfield id="CLRISFEINTLVL" description="Clear Inconsistent-Synch-Field-Error Interrupt Level" begin="28" end="28" width="1" rwaccess="R/W"/>
		<bitfield id="CLRCEINTLVL" description="Clear Checksum-error Interrupt Level (LIN only)" begin="29" end="29" width="1" rwaccess="R/W"/>
		<bitfield id="CLRPBEINTLVL" description="Clear Physical Bus Error Interrupt Level (LIN only)" begin="30" end="30" width="1" rwaccess="R/W"/>
		<bitfield id="CLRBEINTLVL" description="Clear Bit Error Interrupt Level (LIN only)" begin="31" end="31" width="1" rwaccess="R/W"/>
	</register>
	<register id="SCIFLR" acronym="SCIFLR" offset="0xE" page="1" width="32" description="Flag Register" >
		<bitfield id="BRKDT" description="Break-detect Flag (SCI compatible mode)" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="WAKEUP" description="Wake-up Flag" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="IDLE" description="SCI receiver in idle state (SCI compatible mode)" begin="2" end="2" width="1" rwaccess="R/W"/>
		<bitfield id="BUSY" description="Busy Flag" begin="3" end="3" width="1" rwaccess="R/W"/>
		<bitfield id="TIMEOUT" description="LIN Bus IDLE timeout (LIN only)" begin="4" end="4" width="1" rwaccess="R/W"/>
		<bitfield id="TOAWUS" description="Timeout After Wakeup Signal Flag (LIN only)" begin="6" end="6" width="1" rwaccess="R/W"/>
		<bitfield id="TOA3WUS" description="Timeout After 3 Wakeup Signal Flag (LIN only)" begin="7" end="7" width="1" rwaccess="R/W"/>
		<bitfield id="TXRDY" description="Transmitter Buffer Ready Flag" begin="8" end="8" width="1" rwaccess="R/W"/>
		<bitfield id="RXRDY" description="Receiver Buffer Ready Flag" begin="9" end="9" width="1" rwaccess="R/W"/>
		<bitfield id="TXWAKE" description="SCI Transmitter Wakeup Method Select" begin="10" end="10" width="1" rwaccess="R/W"/>
		<bitfield id="TXEMPTY" description="Transmitter Empty Flag" begin="11" end="11" width="1" rwaccess="R/W"/>
		<bitfield id="RXWAKE" description="Receiver Wakeup Detect Flag" begin="12" end="12" width="1" rwaccess="R/W"/>
		<bitfield id="IDTXFLAG" description="Identifier On Transmit Flag (LIN only)" begin="13" end="13" width="1" rwaccess="R/W"/>
		<bitfield id="IDRXFLAG" description="Identifier on Receive Flag" begin="14" end="14" width="1" rwaccess="R/W"/>
		<bitfield id="PE" description="Parity Error Flag" begin="24" end="24" width="1" rwaccess="R/W"/>
		<bitfield id="OE" description="Overrun Error Flag" begin="25" end="25" width="1" rwaccess="R/W"/>
		<bitfield id="FE" description="Framing Error Clag" begin="26" end="26" width="1" rwaccess="R/W"/>
		<bitfield id="NRE" description="No-Response Error Flag" begin="27" end="27" width="1" rwaccess="R/W"/>
		<bitfield id="ISFE" description="Inconsistent Synch Field Error Flag (LIN only)" begin="28" end="28" width="1" rwaccess="R/W"/>
		<bitfield id="CE" description="Checksum error Flag (LIN only)" begin="29" end="29" width="1" rwaccess="R/W"/>
		<bitfield id="PBE" description="Physical Bus Error Flag (LIN only)" begin="30" end="30" width="1" rwaccess="R/W"/>
		<bitfield id="BE" description="Bit Error Flag (LIN only)" begin="31" end="31" width="1" rwaccess="R/W"/>
	</register>
	<register id="SCIINTVECT0" acronym="SCIINTVECT0" offset="0x10" page="1" width="32" description="Interrupt Vector Offset Register 0" >
		<bitfield id="INTVECT0" description="LIN Module reset bit" begin="0" end="0" width="1" rwaccess="R"/>
	</register>
	<register id="SCIINTVECT1" acronym="SCIINTVECT1" offset="0x12" page="1" width="32" description="Interrupt Vector Offset Register 1" >
		<bitfield id="INTVECT1" description="LIN Module reset bit" begin="0" end="0" width="1" rwaccess="R"/>
	</register>
	<register id="SCIFORMAT" acronym="SCIFORMAT" offset="0x14" page="1" width="32" description="Length Control Register" >
		<bitfield id="CHAR" description="Character Length Control bits" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="LENGTH" description="Frame Length Control bits" begin="18" end="16" width="3" rwaccess="R/W"/>
	</register>
	<register id="BRSR" acronym="BRSR" offset="0x16" page="1" width="32" description="Baud Rate Selection Register" >
		<bitfield id="SCI_LIN_PSL" description="Character Length Control Bits" begin="15" end="0" width="16" rwaccess="R/W"/>
		<bitfield id="SCI_LIN_PSH" description="24-Bit Integer Prescaler Select" begin="23" end="16" width="8" rwaccess="R/W"/>
		<bitfield id="M" description="Frame Length Control Bits" begin="27" end="24" width="4" rwaccess="R/W"/>
	</register>
	<register id="SCIED" acronym="SCIED" offset="0x18" page="1" width="32" description="Emulation buffer Register" >
		<bitfield id="ED" description="Receiver Emulation Data" begin="7" end="0" width="8" rwaccess="R"/>
	</register>
	<register id="SCIRD" acronym="SCIRD" offset="0x1A" page="1" width="32" description="Receiver data buffer Register" >
		<bitfield id="RD" description="Received Data" begin="7" end="0" width="8" rwaccess="R/W"/>
	</register>
	<register id="SCITD" acronym="SCITD" offset="0x1C" page="1" width="32" description="Transmit data buffer Register" >
		<bitfield id="TD" description="Transmit data" begin="7" end="0" width="8" rwaccess="R/W"/>
	</register>
	<!-- 1 empty -->  
	<register id="SCIPIO2" acronym="SCIPIO2" offset="0x22" page="1" width="32" description="Pin control Register 2" >
		<bitfield id="RXIN" description="SCIRX pin value" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="TXIN" description="SCITX pin value" begin="2" end="2" width="1" rwaccess="R/W"/>
	</register>      
	<!-- 1 empty -->    
	<!-- 12 empty -->        
	<register id="LINCOMP" acronym="LINCOMP" offset="0x30" page="1" width="32" description="Compare register" >
		<bitfield id="SBREAK" description="Synch Break Extend" begin="2" end="0" width="3" rwaccess="R/W"/>
		<bitfield id="SDEL" description="Sync Delimiter Compare" begin="9" end="8" width="2" rwaccess="R/W"/>
	</register>
	<register id="LINRD0" acronym="LINRD0" offset="0x32" page="1" width="32" description="Receive data register 0" >
		<bitfield id="RD3" description="Receive Buffer 3" begin="7" end="0" width="8" rwaccess="R"/>
		<bitfield id="RD2" description="Receive Buffer 2" begin="15" end="8" width="8" rwaccess="R"/>
		<bitfield id="RD1" description="Receive Buffer 1" begin="23" end="16" width="8" rwaccess="R"/>
		<bitfield id="RD0" description="Receive Buffer 0" begin="31" end="24" width="8" rwaccess="R"/>
	</register>
	<register id="LINRD1" acronym="LINRD1" offset="0x34" page="1" width="32" description="Receive data register 1" >
		<bitfield id="RD7" description="Receive Buffer 7" begin="7" end="0" width="8" rwaccess="R"/>
		<bitfield id="RD6" description="Receive Buffer 6" begin="15" end="8" width="8" rwaccess="R"/>
		<bitfield id="RD5" description="Receive Buffer 5" begin="23" end="16" width="8" rwaccess="R"/>
		<bitfield id="RD4" description="Receive Buffer 4" begin="31" end="24" width="8" rwaccess="R"/>
	</register>
	<register id="LINMASK" acronym="LINMASK" offset="0x36" page="1" width="32" description="Acceptance mask register" >
		<bitfield id="TXIDMASK" description="TX ID Mask bits (LIN only)" begin="7" end="0" width="8" rwaccess="R"/>
		<bitfield id="RXIDMASK" description="RX ID Mask bits (LIN only)" begin="23" end="16" width="8" rwaccess="R"/>
	</register>
	<register id="LINID" acronym="LINID" offset="0x38" page="1" width="32" description="LIN ID Register" >
		<bitfield id="IDBYTE" description="LIN message ID (LIN only)" begin="7" end="0" width="8" rwaccess="R/W"/>
		<bitfield id="IDSLAVETASKBYTE" description="Received ID comparison ID (LIN only)" begin="15" end="8" width="8" rwaccess="R/W"/>
		<bitfield id="RECEIVEID" description="Current message ID (LIN only)" begin="23" end="16" width="8" rwaccess="R"/>
	</register>
	<register id="LINTD0" acronym="LINTD0" offset="0x3A" page="1" width="32" description="Transmit Data Register 0" >
		<bitfield id="TD3" description="TRANSMIT Buffer 3" begin="7" end="0" width="8" rwaccess="R/W"/>
		<bitfield id="TD2" description="TRANSMIT Buffer 2" begin="15" end="8" width="8" rwaccess="R/W"/>
		<bitfield id="TD1" description="TRANSMIT Buffer 1" begin="23" end="16" width="8" rwaccess="R/W"/>
		<bitfield id="TD0" description="TRANSMIT Buffer 0" begin="31" end="24" width="8" rwaccess="R/W"/>
	</register>
	<register id="LINTD1" acronym="LINTD1" offset="0x3C" page="1" width="32" description="Transmit Data Register 1" >
		<bitfield id="TD7" description="TRANSMIT Buffer 7" begin="7" end="0" width="8" rwaccess="R/W"/>
		<bitfield id="TD6" description="TRANSMIT Buffer 6" begin="15" end="8" width="8" rwaccess="R/W"/>
		<bitfield id="TD5" description="TRANSMIT Buffer 5" begin="23" end="16" width="8" rwaccess="R/W"/>
		<bitfield id="TD4" description="TRANSMIT Buffer 4" begin="31" end="24" width="8" rwaccess="R/W"/>
	</register>
	<register id="MBRSR" acronym="MBRSR" offset="0x3E" page="1" width="32" description="Baud Rate Selection Register" >
		<bitfield id="MBR" description="Received Data" begin="12" end="0" width="13" rwaccess="R/W"/>
	</register>
	<!-- 8 empty -->        
	<register id="IODFTCTRL" acronym="IODFTCTRL" offset="0x48" page="1" width="32" description="IODFT for LIN" >
		<bitfield id="RXPENA" description="Analog Loopback Via Receive Pin Enable" begin="0" end="0" width="1" rwaccess="R/W"/>
		<bitfield id="LPPENA" description="Module Loopback Enable" begin="1" end="1" width="1" rwaccess="R/W"/>
		<bitfield id="IODFTENA" description="IO DFT Enable Key" begin="11" end="8" width="4" rwaccess="R/W"/>
		<bitfield id="TXSHIFT" description="Transmit Delay Shift" begin="18" end="16" width="3" rwaccess="R/W"/>
		<bitfield id="PINSAMPLEMASK" description="TX Pin Sample Mask" begin="20" end="19" width="2" rwaccess="R/W"/>
		<bitfield id="BRKDTERRENA" description="Break Detect Error Enable (SCI compatibility mode)" begin="24" end="24" width="1" rwaccess="R/W"/>
		<bitfield id="PERRENA" description="Parity Error Enable (SCI Compatiblity mode)" begin="25" end="25" width="1" rwaccess="R/W"/>
		<bitfield id="FERRENA" description="Frame Error Enable (SCI Compatiblity mode)" begin="26" end="26" width="1" rwaccess="R/W"/>
		<bitfield id="ISFERRENA" description="Inconsistent Synch Field Error Enable (LIN mode)" begin="28" end="28" width="1" rwaccess="R/W"/>
		<bitfield id="CERRENA" description="Checksum Error Enable (LIN mode)" begin="29" end="29" width="1" rwaccess="R/W"/>
		<bitfield id="PBERRENA" description="Physical Bus Error Enable (LIN mode)" begin="30" end="30" width="1" rwaccess="R/W"/>
		<bitfield id="BERRENA" description="Bit Error Enable (LIN mode)" begin="31" end="31" width="1" rwaccess="R/W"/>
	</register>
	
</module>

    Best Regards,

    Marlyn