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TMS320F28335: ePWM timing issue: How to explain CTR=CMP?

user4811888
Intellectual 530 points

Part Number: TMS320F28335

Hi expert,

I'm really confused by descriptions in C2000 TRM about how PWM will toggle, as it is said "CTR=CMP" only.

However as you know, digital circuity is combined by several synchronous sequence logic gates with CLK, it cannot be simplified by "CTR=CMP" without considering about sequence timing.

Let us consider this kind of condition: shadow resister disabled, refresh CMP immediately after data is ready.

See below four examples I drew, are they all correct by my understanding? So what is the exact criteria of PWM toggle?

  • 0
    Intellectual 530 points

    Hello,

    Any reply or suggestions here?

  • 0 in reply to user4811888
    TI__Mastermind 42195 points

    Hello, 

    The comment in the TRM is to say that the CMPx registers will not trigger provided that a TBCTR value greater than the CMPx register. If your CMPA value is updated from 10 to 4 when TBCTR =5 then The CMPA event will not happen during that PWM period.

    To answer your exact question on wither or not the the PWM's output level shifts on the exact clock edge, or if this is delay one cycle: I believe the edge transitions exactly as TBCTR is updated to the value which is equal to CMPx.

    1. Will trigger, but not as you have drawn it, it will trigger earlier at the beginning of TBCTR= CMPx
    2. This will trigger but earlier than indicated.
    3. This is a race condition, I do not know off of the top of my head which event occurs first CMPx update or CMPx compare to TBCTR. If you need the answer to this I can inquire.
      1. I believe that CMPx is updated then CMPx is compared to TBCTR, but like I said before i'm not sure.
    4. This again is a race condition, provided that the CMPx value is updated before the CMPx comparison to TBCTR then no event will happen. 

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 530 points

    Hi Cody,

    Thanks for your kind answer, it seems to me that the digital TBCTR=CMPx comparator is a combinational logic(asynchronous event with CLK), right?

    If it is true, actually there's no sequence between CMPx update and CMPx compare to TBCTR, as comparison event is executing as always.

  • 0 in reply to user4811888
    TI__Mastermind 42195 points

    Correct, I do not thing the comparison is gated by the clock. Of course the TBCTR will increment synchronously to the clock, so the output will in fact look synchronous.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 530 points

    Thanks Cody, understand.

    But my last question is, why cannot we make the toggle condition as TBCTR>CMPx instead of TBCTR=CMPx?

    This can help us avoid the wrong condition in my picture 4.

  • 0 in reply to user4811888
    TI__Mastermind 42195 points

    Functionally this can be done.

    However it creates a wide verity of boundary conditions, for example phase shifting or synchronizing can create unexpected wider pulses. It can also create narrower pulses too, but its the wider pulses which are typically more prone to causing damage to FETs. It all depends on the counter values you are shifting from and to. This can be very difficult to predict when Frequency, Duty and Phase are all changing.

    Regards,
    Cody 

  • 0 in reply to Cody Watkins
    Intellectual 530 points

    Could understand to some degree, it is hard to take care of all of boundary conditions by a fixed criteria when freq, duty, phase are all changing.

    Unexpected pulses could be observed in kinds of special conditions. Thus, could I say that TI doesn't recommend refresh immediately?

  • +1 in reply to user4811888
    TI__Mastermind 42195 points

    I can only comment for c2000 devices. Yes in almost all cases immediate load mode is not recommended, Shadow loading is highly recommended unless the user has very thoroughly understood their use case.