TMS320F28388D: Register for Selecting between GPTRIP or Sync0/1

You're looking for SYNCIN_EXTSYNC2_SEL in the registers?

Nima

Hi Nima,

Yes, either SYNCIN_EXTSYNC1_SEL or SYNCIN_EXTSYNC2_SEL. I am using CM to run the EtherCAT, and trying to sync ePWM with EtherCAT Sync0.

Thanks,

Lily

I see. I searched for the Signal in the TRM and could not find it either.

Vivek Singh Do you know where this comes from in the ETHERCAT section?

Hi Nima,

Any update on this subject?

Thanks,

Lily

Still tracking this down with the expert of Ethercat.

Hi Nima,

Any update?

BR,

Lily

Waiting for the expert to respond! Sorry for the delay.

Hi Nima,

Thanks for the reply. I've tried the option described for 'EPWMSYNCINSEL' (Sync0, 0x1A) . But it didn't work as I expected.

I have ESC assigned to CM. CPU1 controls EPWM.

EPWM sync to EtherCAT Sync0 when output Sync0 to GPIO127, then assign GPIO127  to INPUTXbar5. But EPWM does not sync to Sync0 when source  'SYNC_IN_SRC_ETHERCAT_SYNC0' directly. Please advise.

/********************* XBar-input Extsync1 to xbar5 **********************/
InputXbarRegs.INPUT5SELECT = 127; //GPIO127 for ECAT Sync0

// EPwm1Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_INPUTXBAR_OUT5; //Xbar5

EPwm1Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_ETHERCAT_SYNC0; // EtherCAT Sync0
EPwm2Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_SYNCOUT_EPWM1;
EPwm3Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_SYNCOUT_EPWM1;

Best Regards,

Lily.

Ethercat syncs EPWM. Not EPWM sync ethercat.

That's correct. EtherCAT Sync0 is the source of EPWM SYNCIN. I wanted the EPWM phase lock to EtherCAT Sync0. But it did not happen when the following is selected.

EPwm1Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_ETHERCAT_SYNC0; // EtherCAT Sync0 

Thanks,

Lily

Make sure to check your EPWM phase settings.

Nima

Hi Nima,

I believe the EPWM phase settings are correct, because the EPWM phase locked to EtherCAT Sync0 when output EtherCAT Sync0 to GPIO127, then assign GPIO127  to INPUTXbar5.

Worked:

InputXbarRegs.INPUT5SELECT = 127; //GPIO127 for ECAT Sync0

EPwm1Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_INPUTXBAR_OUT5; //Xbar5  

Did not Work: 

EPwm1Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_ETHERCAT_SYNC0; // EtherCAT Sync0 

Please refer to my post a day ago.

Thanks,

 Lily

So the direct source does not work while INPUTXABR5 + GPIO works?

That's correct.

Hi Lily,

Can you confirm that value of EPwm1Regs.EPWMSYNCINSEL.bit.SEL field is correct by looking into CCS register view after execution of "EPwm1Regs.EPWMSYNCINSEL.bit.SEL = SYNC_IN_SRC_ETHERCAT_SYNC0; // EtherCAT Sync0" code.

Regards,

Vivek Singh

Hi Vivek,

Thanks for looking into this!

Here is EPWMSYNCINSEL reading:

Best Regards,

Lily

Thank you for the confirmation. We'll check this further with our design team and get back to you early next week.

Regards,

Vivek Singh

Thank you Vivek!

Have a great weekend!

Lily

Hi Ginily,

Our design team confirm that this should work as expected. Will it be possible for you to create a sample project which we can run on our setup to reproduce the issue ?

Regards,

Vivek Singh

Ginily,

Please provide the sample project if possible.

Nima

Thanks Nima,

I am using inputxbar5 for ECAT sync0 as EPWM sync temporally. I wouldn't be able to provide a sample project soon due to my busy schedule. It would be nice if TI has sample projects I can refer to.

Thanks,

Lily

Understood, please provide the example when possible.

Thank you for understanding.

BR,

Lily