C6472 (porting MIDAS OCT from C6678) EDMA3_RM_open returns 0xffffff62

Stefanos A.

Other Parts Discussed in Thread: MIDAS

Hello,

I am trying to port the MIDAS OCT demo from the C6678 to the C6472 and I am now stuck at an issue that I cannot seem to fix: a call to RMAN_assignResources fails with status=7 (IRES_ENORESOURCE).

The trace log indicates that the issue stems from a call to EDMA3_RM_open which fails with error 0xffffff62, which apparently translates into EDMA3_RM_E_INVALID_PARAM. The relevant part of the trace log reads:

[+2] EDMA3_getResourceManager> Opening System Resource Manager Handle
[+E] openRMHandle> Enter (scratchId=-1, sem=0x9105828)
[+2] openRMHandle> System RM handle requested
[+7] openRMHandle> Error opening RM handle requested, status 0xffffff62
[+X] openRMHandle> Exit (handle=NULL)
[+7] EDMA3_getResourceManager> Error opening System Resource Manager Handle

One thing I find curious is that scratchId is -1, while I only request scratchId 0 (I don't know if that is normal or not).

Another possible issue might stem from the EDMA3_RM_InstanceInitConfig structure that I am currently using. I have copied this verbatim from EDMA3_C6472_cfg.c and I have no idea if I need to change something in there (I haven't been able to find any documentation on the hex values in that file.) How and when am I supposed to modify this file?

I am building with C6000 compiler v7.4.2, XDCTools 3.24.5.48 and linking with FC 3.23.1.14, CE 3.23.0.07, EDMA3 2.11.6, XDAIS 7.23.0.06 and SYS/BIOS 6.34.3.19. My trace log, SYS/BIOS and EDMA3 configurations are attached.

I would be happy for any ideas or advice on this issue!

2110.trace.txt

1234.bios.cfg

Fullscreen 4578.edma3_config.c Download

/**
 *  @file   edma3_config.c
 *  @brief EDMA3's InstanceInitConfig
 *
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <xdc/std.h>
#include <ti/sdo/fc/edma3/edma3_config.h>
#include <ti/sdo/edma3/rm/edma3_rm.h>

#define NUM_EDMA3_INSTANCES         1u

EDMA3_RM_InstanceInitConfig C6472_config [NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
{
    {
      {
        /* Resources owned by Region 0 */
         /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x000000FFu, 0x00000000u},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000001u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x000000FFu, 0x00000000u},

        /* Resources reserved by Region 0 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0    63     32 */
        {0xFFFF0000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0    63     32 */
        {0xFFFF0000u, 0x00000000u},
      },

      {
        /* Resources owned by Region 1 */
        /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x0000FF00u, 0x00000000u},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000002u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x0000FF00u, 0x00000000u},

        /* Resources reserved by Region 1 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0    63     32 */
        {0xFFFF0000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0    63     32 */
        {0xFFFF0000u, 0x00000000u},
      },

      {
        /* Resources owned by Region 2 */
         /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0x000000FFu},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000004u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0x000000FFu},

        /* Resources reserved by Region 2 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0    63     32 */
        {0xFFFF0000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0    63     32 */
        {0xFFFF0000u, 0x00000000u},
      },

      {
        /* Resources owned by Region 3 */
         /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0x0000FF00u},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000008u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0x0000FF00u},

        /* Resources reserved by Region 3 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0     63    32 */
        {0xFFFF0000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0     63    32 */
        {0xFFFF0000u, 0x00000000u},
      },

      {
        /* Resources owned by Region 4 */
         /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0x00FF0000u},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000008u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0x00FF0000u},

        /* Resources reserved by Region 4 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0     63    32 */
        {0xFFFF0000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0     63    32 */
        {0xFFFF0000u, 0x00000000u},
      },

      {
        /* Resources owned by Region 5 */
         /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0xFF000000u},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000008u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0xFF000000u},

        /* Resources reserved by Region 5 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0     63    32 */
        {0xFFFF0000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0     63    32 */
        {0xFFFF0000u, 0x00000000u},
      },

      {
        /* Resources owned by Region 6 */
         /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},

        /* Resources reserved by Region 6 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},
      },

      {
        /* Resources owned by Region 7 */
         /* ownPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* ownDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},

        /* ownQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* ownTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},

        /* Resources reserved by Region 7 */
        /* resvdPaRAMSets */
        /* 31     0     63    32     95    64     127   96 */
        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 159  128     191  160     223  192     255  224 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 287  256     319  288     351  320     383  352 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
        /* 415  384     447  416     479  448     511  480 */
         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},

        /* resvdDmaChannels */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},

        /* resvdQdmaChannels */
        /* 31     0 */
        {0x00000000u},

        /* resvdTccs */
        /* 31     0     63    32 */
        {0x00000000u, 0x00000000u},
      }
    }
};



#if 0

// Todo: this is copied verbatim from the C66 implementation.
// Find out wth these bitmasks do and ensure they are valid.
// This structure is automagically accessed by the XDC configuration
// script.

//EDMA3_InstanceInitConfig C6678_config =
EDMA3_InstanceInitConfig C6472_config =
      {

        /* Resources owned by Region 0 */

         /* ownPaRAMSets */

        /* 31     0     63    32     95    64     127   96 */

        {0xFFFFFFFF, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,

        /* 159  128     191  160     223  192     255  224 */

         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,

        /* 287  256     319  288     351  320     383  352 */

         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,

        /* 415  384     447  416     479  448     511  480 */

         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},



        /* ownDmaChannels */

        /* 31     0     63    32 */

        {0xFFFFFFFF, 0xFFFFFFFFu},



        /* ownQdmaChannels */

        /* 31     0 */

        {0x00000001u},



        /* ownTccs */

        /* 31     0     63    32 */

        {0xFFFFFFFFu, 0xFFFFFFFFu},



        /* Resources reserved by Region 0 */

        /* resvdPaRAMSets */

        /* 31     0     63    32     95    64     127   96 */

        {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,

        /* 159  128     191  160     223  192     255  224 */

         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,

        /* 287  256     319  288     351  320     383  352 */

         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,

        /* 415  384     447  416     479  448     511  480 */

         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},



        /* resvdDmaChannels */

        /* 31     0    63     32 */

        {0x00000000u, 0x00000000u},



        /* resvdQdmaChannels */

        /* 31     0 */

        {0x00000000u},



        /* resvdTccs */

        /* 31     0    63     32 */

        {0x00000000u, 0x00000000u},

      };

#endif

over 12 years ago

0 Uday over 12 years ago

TI__Expert 4920 points

Hi Stefanos

I am looking into this and will get back to you with what might be going wrong.

In the meantime here is some information that you might find useful wrt your question on EDMA RM:

The EDMA3_RM_InstanceInitConfig is a structure that is used to specify which EDMA3 resources are owned and reserved by the EDMA3 driver instance. Once you install the EDMA3 LLD, you can navigate through the relevant documentation from CCS, by going to Help-->Help Contents-->EDMA3 Low Level Driver xx.xx.xx. Here you'll find the EDMA3 Resource Manager user guide as well as the API references, which explain the EDMA3_RM_InstanceInitConfig, for example. The EDMA3 Driver User Guide is also available through that interface.The header files in the EDMA3 LLD also have relevant information. I believe MIDAS OCT uses the 'Framework Component' software component called ECPY. For your reference, here's some information I've scouted on the hex values:

ownDmaChannels: The bitmap(s) which indicate the DMA channels owned by this instance of the Resource Manager. For example, a '1' at bit position 24 indicates that this instance of the Resource Manager owns Channel Id 24. Later when a request is made based on a particular Channel Id, the Resource Manager will check first if it owns that channel. If it does not own it, Resource Manager returns error EDMA3_RM_E_RES_NOT_OWNED.

ownPaRAMSets: PaRAM Sets which are to be used by this Region

ownQdmaChannels: The bitmap(s) which indicate the QDMA channels owned by this instance of the Resource Manager

ownTccs: The bitmap(s) which indicate the TCCs owned by this instance of the EDMA3 Driver

resvdPaRAMSets: PaRAM Sets which are reserved by this Region

resvdDmaChannels: The bitmap(s) which indicate the DMA channels reserved by this instance of the EDMA3 Driver. E.g. A '1' at bit position 24 indicates that this instance of the EDMA3 Driver reserves Channel Id 24. These channels are reserved and may be mapped to HW events, these are not given to 'EDMA3_DRV_DMA_CHANNEL_ANY' requests.

resvdQdmaChannels: The bitmap(s) which indicate the QDMA channels reserved by this instance of the EDMA3 Driver E.g. A '1' at bit position 1 indicates that this instance of the EDMA3 Driver reserves QDMA Channel Id 1. These channels are reserved for some specific purpose, these are not given to 'EDMA3_DRV_QDMA_CHANNEL_ANY' request

resvdTccs: TCCs which are reserved by this Region

0 Stefanos A. over 12 years ago in reply to Uday

Prodigy 150 points

Thank you for the explanation, this helped a lot!

In case someone else encounters the same issue, the problem lay here:

EDMA3_PARAMS.controllerId = 1;

The C6472 megamodule only contains a single EDMA3 controller. The line above would try to initialize the second controller, which resulted in invalid memory being copied from the EDMA3_RM_InstanceInitConfig structure and random failures later on. The solution, of course, is to use:

EDMA3_PARAMS.controllerId = 0;

Processors

Processors forum

C6472 (porting MIDAS OCT from C6678) EDMA3_RM_open returns 0xffffff62