TMS320F28377D: special PWM pattern

Hello Mauro,

Could you use a single PWM time-base configured in up-down count mode to produce both pulse trains?  The CMPA/B registers would be set close to the zero & period events.  You would have to halve the PWM clock frequency to 50MHz to reach the lower (800Hz) PWM frequency, otherwise it seems straightforward.

The attached diagram shows how this might be done to control a 2-phase boost topology.  This way you are guaranteed to have the right phase relationship at all frequencies.  Would this work?

Regards,

Richard

2-phase PWM.pdf

The problem is that there is
NO single instruction to change simultaneously TBPRD and CA (compare A).

So there colud be a situation in which the PWM use a period that not match CA (compare A)
and so I have pain that PWM will be not the desired.

I have no interrupt on zero match, I have a 1ms- periodic ISR that manages PWM

ok, Tomorrow I read Chapter 14 I try to implement the solution, I verify it and I click on "Verify Answer", thankyou in advice

the code work properly,

here the waveforms without GLDCTL (sometimes, when there is mismatch between TBPRD and CMPB)

here with GLDCTL

my code

void doublePulse_Setup(float Ton)
{
	// SPRUHM8C–December 2013–Revised December 2014

	EALLOW;

		CpuSysRegs.PCLKCR2.bit.EPWM4		= 1;				// enable clock

		asm(" RPT #4 || NOP");

		// set time base mode and behaviour

		EPwm4Regs.TBCTL.bit.FREE_SOFT		= 2;				// p1563, PWM is ON even in emulator break mode
		EPwm4Regs.TBCTL.bit.CTRMODE			= TB_COUNT_UPDOWN;	// p1564
		EPwm4Regs.TBCTL.bit.HSPCLKDIV		= TB_DIV1;			// p1564

		// set pattern for out A

		EPwm4Regs.AQCTLA.bit.CAD			= AQ_SET;			// p1594
		EPwm4Regs.AQCTLA.bit.CAU			= AQ_CLEAR;			// p1594

		// set pattern for out B

		EPwm4Regs.AQCTLB.bit.CBD			= AQ_CLEAR;			// p1597
		EPwm4Regs.AQCTLB.bit.CBU			= AQ_SET;			// p1597

		// set Ton

		EPwm4Regs.CMPA.bit.CMPA				= 0.5*(100e6*Ton-1);// p1609

		// global syncronous load CMPB,TBPRD su CNT_ZRO

		EPwm4Regs.GLDCFG.bit.CMPB_CMPBHR	= 1;				// p1589
		EPwm4Regs.GLDCFG.bit.TBPRD_TBPRDHR	= 1;				// p1589
		EPwm4Regs.GLDCTL.bit.GLD			= 1;				// p1587
		EPwm4Regs.GLDCTL.bit.OSHTMODE		= 1;				// p1586

	EDIS;
}

float doublePulse_SetFrequency(float Fvco, float Tdb)
{
	Uint16 TBPRD			= 0.5*100e6/Fvco - 1;
	Uint16 DBT				= 100e6*Tdb;

	EPwm4Regs.TBPRD			= __lmax(TBPRD, 2*EPwm4Regs.CMPA.bit.CMPA + DBT);	// "__lmax" p140 SPRU514G– December 2013
	EPwm4Regs.CMPB.bit.CMPB	= EPwm4Regs.TBPRD - EPwm4Regs.CMPA.bit.CMPA;

	// Enable Reload Event in One Shot Mode
	// e2e.ti.com/.../571072

	EALLOW;

		EPwm4Regs.GLDCTL2.bit.OSHTLD		= 1;				// p1613

	EDIS;

	return 0.5*100e6/(1.0+EPwm4Regs.TBPRD);
}