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Tool/software: Code Composer Studio
In the SDFM module of 28377d ,the Sdfm1Regs.SDIFLG.bit.MF1==1,I can't clear this flag。In the datasheet this error means the clock loss。The clock is 20M。what happend?Thank you!
Hi,Manoj
This is the GPIO configuration of SD-C and SD-D,The another configuration is same as the example code available in controlSuite, C:\ti\controlSUITE\device_support\F2837xD\v210\F2837xD_examples_Cpu1\sdfm_pwm_sync_cpu.
Then I test the C:\ti\controlSUITE\device_support\F2837xD\v210\F2837xD_examples_Cpu1\sdfm_pwm_sync_cpu. when I stop simulation, it still has the clock error
YES,when I stop simulation the EPWM TBcount stoped. How I set the configuration if I want the EPWM didn't stop when I stop the simulation.thank you!
regards
shook
Shook,
Check whether TBCTL.FREE_SOFT = 3 (PWM register), this will make sure that PWM will continue toggling when you hit a breakpoint.
Regards,
Manoj