CCS/TMS320F28379D: SYSTEM-CLOCK-timer period 801 TBCLKs

Hi,

kudithi nageswararao said:

according to this value i should get the value of TBPRD = 5000(SYSCLKOUT/PWM freq)

How do you compute this value? It should be using this formula: Please verify your TBCLK value which is derived from SYSCLK.

Regards,

Gautam

Hi Kudithi,

The TBCTL.CTRMODE is set as up-down. Hence the TBPRD = fTBCLK/(2 * fPWM).
In this device,
max SYSCLKOUT = 200 MHz,
max EPWMCLK = 100MHz,
TBCLK = EPWMCLK/(HSPCLKDIV * CLKDIV)

Thanks
Vasudha

Vasudha Bhadoria said:

The CLK_CFG_REGS.PERCLKDIVSEL.EPWMCLKDIV is set to /2 on reset. If the sysclk is getting set to 100MHz, try changing the EPWMCLKDIV to 0 to keep EPWMCLK = SYSCLK / 1.

Exactly! For TBPRD = 2500; HSPCLKDIV & CLKDIV should be /1.

Hi Vasudha
i am using LAUNCHXL-F28379D.

this is my program.....where i have to write instructions belongs for PLL sysclk settings in my programing to get 100MHz.

#include "F28x_Project.h"
#define PWM_Prd 1250;
#define Phi 0;
void InitEPwm1Example(void);
__interrupt void epwm1_isr(void);
void main(void)
{
InitSysCtrl();

CpuSysRegs.PCLKCR2.bit.EPWM1=1;

InitEPwm1Gpio();

DINT;

InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW;
PieVectTable.EPWM1_INT = &epwm1_isr;

EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;

InitEPwm1Example();

EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;

IER |= M_INT3;

PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;

EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

for(;;)
{
asm (" NOP");
}
}

__interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPHS.bit.TBPHS = 0;

EPwm1Regs.ETCLR.bit.INT = 1;

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 1250; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0; // Clear counter
// // Set Compare values0 //
EPwm1Regs.CMPA.bit.CMPA = 1250; // Set compare A value
EPwm1Regs.CMPB.bit.CMPB = 1250;
// // Setup counter mode //
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading




EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;



// // Setup shadowing //
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set actions //
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up
// count
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Clear PWM1A on event A,
// down count

EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up
// count
EPwm1Regs.AQCTLB.bit.ZRO= AQ_SET; // Clear PWM1B on event B,
// down count

// // Interrupt where we will change the Compare Values //
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event


}

Hi Kudithi,

Since it's a launchpad, pllsysclk is getting set as 100MHz in InitSysCtrl() as external crystal is of 10MHz in launchpad. Try adding the below line to set the epwmclk div to 0 to make the epwmclk = pllsysclk/1.

ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;

Thanks
Vasudha

Hi Vasudha
thank you
Case:1
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm1Regs.TBCTL.bit.CLKDIV = 0;

if i used like this i got 10KHz for TBPRD=2500;

Case:2
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 1;
EPwm1Regs.TBCTL.bit.CLKDIV = 1;

if i used like this i got 2.5KHz for TBPRD=2500;
it means x/4

Case:3
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

if i used like this i got 10KHz for TBPRD=2500;

case:4
according to you suggestion :if i used like this

ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;

i got 10KHz for TBPRD=2500;


ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=1;

if i used like this i got 5KHz for TBPRD=2500;

ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=TB_DIV1;

if i used like this i got 10KHz for TBPRD=2500;


so i could't understand the how to set TBPRD with SYSCLK

Hi Nageswara,

Assuming the sysclk is 100 MHz. You need to configure all the following:

EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;  // means  /1

EPwm1Regs.TBCTL.bit.CLKDIV = 0;          // means /1

ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;  // means /1 of pllsysclk

 

With the above setting:

sysclk = 100 MHz

epwmclk = sysclk/epwmclkdiv  = 100 MHz

tbclk = epwmclk/(hspclkdiv*clkdiv) = 100 MHz

tbprd = 100MHz/(2 * 20KHz) = 2500

Also Case 1 & Case 3 are same as TB_DIV1 should be 0.

For Case 4 what are the hspclkdiv & clkdiv values ?

Thanks

Vasudha

Hi Vasudha
thank you very much now i got it.


Case:1
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm1Regs.TBCTL.bit.CLKDIV = 0;

if i used like this i got 20KHz for TBPRD=2500;

Case:2
//ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV =0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm1Regs.TBCTL.bit.CLKDIV = 0;

if i used like this i got 20KHz for TBPRD=2500;


Case:3
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

if i used like this i got 20KHz for TBPRD=2500;

but

how i can get 20KHz for TBPRD=5000?

For up-down counter mode, TBPRD = 2500 for 20KHz.
You can change the ctr mode to up or down, then TBPRD = 4999 will give 20KHz.