• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 83 subscribers
  • Views 2216 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28069: Glitch on rising edge of I2C or GPIO

Darren Jenkins
Genius 11456 points
Part Number: TMS320F28069

C2000 Team,

We have a customer observing something unexpected on the I2C Clock pin and the same kind of thing on a GPIO pin.

They looked at the I2C Clock and saw a spike on the rising edge.  They scoped a different pin, configured as output, toggling with GPIO_writePin(), and see the same spike. (This is an F28069, and they have modified DriverLib from F2837x to support the F28069.) On the GPIO pin, the only thing connected to that trace is a 100 kOhm pull-up. 

I’m attaching a couple scope plots so you can see what I mean.  Is this something familiar?

Thanks,

Darren

  • 0
    Guru 30330 points
    Darren,

    A few comments:
    1. Can you share the GPIO configuration for each of the pins that are shown?
    2. On the F28069, there is no specific open drain configuration possible on the GPIOs. The available open-drain capabilities are only present when the GPIO is assigned to the I2C module.
    3. Can you confirm that they are seeing this on the F28069?
    4. can you share the GPIO_writePin() function for the F28069 that you are toggling the GPIO with?

    I am getting a setup together to try to replicate this.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    TI__Genius 11456 points
    Hi Mark,

    I need to correct my original post. The problem is with the F28379S. They also use an F28069, but do not see the problem there.

    They see the problem with F28379S using Driverlib when toggling a GPIO as Open Drain and when the pin is configured as I2C. They are using the existing Driverlib software. I'll ask for the code.

    Thanks,
    Darren
  • 0 in reply to Darren Jenkins
    Guru 30330 points
    Thanks Darren! That clears up a lot of the questions I have. I have been able to replicate the behavior and am in discussions to get to the bottom of it.

    Is this causing any issues with the customer design, or is this just a "huh, that's weird" kind of situation?

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    TI__Genius 11456 points
    Hi Mark,

    Glad to hear you've been able to replicate it.

    This isn't causing specific problems. They saw the way the I2C Clock rises with potentially two rising edges and were concerned it could cause a problem in the future, possibly under stress conditions.

    Thanks,
    Darren
  • 0 in reply to Darren Jenkins
    Guru 30330 points
    Darren,

    A few followup questions:
    - Please confirm if open-drain output is enabled while the pin is using I2C.
    - Please share the GPIO configuration for each of the pins that they have seen the behavior.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    TI__Genius 11456 points
    Mark,

    Here are the lines of code that are being used to setup and drive the GPIO. In this case, it's GPIO 121 being configured as a GPIO with Open Drain output.

    #include "Device.h"
    #include "GlobalPrototypes.h"
    #include "Gpio_defines.h"

    GPIO_SetupPinOptions(121, GPIO_OUTPUT, GPIO_OPENDRAIN | GPIO_ASYNC);
    GPIO_SetupPinMux(121, GPIO_MUX_CPU1, 0);
    GPIO_WritePin(121, 1);

    Since there are many other lines (and layers) of code, this was the easiest way to share the configuration to show when the problem happens. It also happens in an I2C configuration. Is this sufficient or do you need to know specifically about Open Drain in I2C mode?

    Thanks,
    Darren
  • 0 in reply to Darren Jenkins
    Guru 30330 points

    Darren,

    Thanks for the additional information. I have used the same code to replicate the behavior.

    To summarize (and close this thread):

    On F2837xD, F2837xS, F2807x, and F28004x devices, a brief high-going glitch of ~6-8ns will occur on the rising edge transition of I2C SDA and I2C SCL, as well as the open-drain output of the GPIO (GPxODR = 1). The magnitude of the glitch will vary based on which pin is used, load, and trace capacitance . The magnitude of the glitch may be filtered by adding some RC to the signal trace, including a series resistor and a capacitor placed between the signal and GND.  The values for these components will be dependent upon the same conditions listed above (pin #, load, trace cap). Refer to the following image. This is GPIO105 configured as I2CSCLA, with a 10k pullup to VDDIO on F28379D. 

    Regards,

    Mark