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Original question:

TMS320C28346: McBSP Clock Stop Mode Configuration

TMS320C28346: McBSP Clock Stop Mode Configuration

Terry Bush
Prodigy 50 points
Part Number: TMS320C28346


I understand that the existing clock stop mode configuration is undefined and cannot provide guaranteed operation. The McBSP is being used as the SPI master so I will configure CLKSTP/CLKXP/CLKRP as 1100b (as defined state per table 6-2) in the revision.

I would like further clarification on CLKRM bit. I understand that signal is irrelevant since CKLSTP = 11b. However, I still wonder if the existing design (MCLKR pin configured as an output pin while also being driven from an unsynchronized external source) could possibly affect proper operation of McBSP internal chip hardware (noise interference, saturation of MOS gates, latch-up, etc..) and contribute to data receive errors. Note that the frame sync pin is also being driven from an external source. I intend to modify the configuration to define both of these pins as input pins (CLKRM=0 and FSRM=0) even though I don't use the signals. This is so that I do not need to change hardware boards in existing systems to remove external drive signals; simpler to download new firmware version to eliminate drive signal collision condition on these pins.

  • 0
    Guru 30330 points
    Terry,

    I am very confused with the configuration of your hardware and software.

    You have said that you are using the SPI mode of McBSP, but you have all 6 McBSP signals connected? Can you share a schematic snipped of the HW? if you cannot share a screenshot, please provide a table of all of the McBSP pins and what they are connected to on the PCB. It sounds like there is a lot of confusion in what is needed for the SPI mode to work. In SPI mode of the McBSP, only MFSX, MCLKX, MDX, and MDR pins need to be connected.

    A simple way to completely alleviate this issue if all 6 pins are connected externally is to simply configure the GPIOs of MCLKR and MFSR to be GPIO input pins. In this configuration, the McBSP MCLKR and MFSR signals (into the module) are completely isolated from GPIO boundary. If these are not used in the application, leaving them as inputs will remove any chance of interfering with the McBSP module itself. You would not need to touch hardware on this revision, but I highly recommend changing it in the next version. You would gain two GPIOs doing this while eliminating any noise sources.

    Having the MCLKR and MFSR pins connected while using the SPI mode of the McBSP is not a tested or valid usage. I cannot confirm if having these signals being connected will ever cause data issues, but it would not surprise me.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Guru 30330 points
    Following up here, I have requested additional information from design in this situation and will update this thread.

    Terry, Please clarify my questions above. I think a simplified connection diagram will clear up some of my confusion.

    Please also just change the GPIO mux configuration to make the GPIOs currently used for MCLKR and MFSR, to be configured as GPIO inputs. This will eliminate any possibility of external signals on unused McBSP pins potentially causing McBSP errors.
  • 0 in reply to Mark Labbato
    Guru 30330 points
    Terry,

    Do you have any additional information or concerns with this topic?

    -Mark
  • 0 in reply to Mark Labbato
    Prodigy 50 points

    Mar,

    I have no additional concerns.

    We have implemented the changes you suggested (reconfigure Clock Stop Mode to recommended setting per guide spec and configure unused pins as GPIO)

    Testing is ongoing and system is performing as expected.

    Thank you for all the help.

    Terry

     

  • 0 in reply to Terry Bush
    Guru 30330 points
    Terry,

    Glad to hear that it is performing as expected.

    Please don't hesitate to post again in the future if you find additional concerns.

    -Mark