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TMS320C28346: McBSP Clock Stop Mode Configuration

Terry Bush
Prodigy 50 points
Part Number: TMS320C28346


Trouble shooting an existing design using McBSP port to communicate to and SPI device.

The Clock Stop Mode is configured as follows: CLKSTP = 11b , CLKXP = 0, CLKRP = 0.

This is not a setting defined in table 6-2 of reference guide for McBSP (SPRUG80A rev Aug/2011).

Question #1 - How will the serial port perform with this undefined configuration? We are seeing occasional communication errors and want to know if this is root cause.  

Question #2 - The MCLKR (receive clock) is programmed as an output but there is an external buffer driving the pin as a clock input. Could this make the port malfunction and produce errors?

Question #3 - Will configure pin to be an input (CLKRM=0) in re-design. Will enabling clock stop mode "force" the pin to be an output overriding the CLKRM configuration bit? (literature seems to imply this, but not clear).

 

  • 0
    Guru 30330 points

    Terry,

    I hope that I can help out here:

    1. This is an undefined state. There is probably a chance that it mostly works in your system, but we do not guarantee that it will.  In your revision, please align to the appropriate scheme as mentioned in Table 6-2.

    2. Are you set up as the SPI master or slave. In either case, the CLKX pin is the SPICLK pin, and the CLKR pin is not used. See Tables 6-3 and 6-4: the CLKXM bit describes how the internal MCLKR path is driven by CLKX internally.

    3.  CLKRM bit is not necessary. since you are setting the CLKXM to 1 and configuring CLKSTP as 10b or 11b, the CLKRM is irrelevant. This is stated in the CLKXM bit definition (Table 11-16) : 

    Regards,

    Mark

  • 0 in reply to Mark Labbato
    TI__Genius 16820 points
    Customer follow up questions have been addressed in the following post:
    e2e.ti.com/.../682264
  • 0 in reply to Lenio Cacula
    TI__Genius 16820 points
    I understand that the existing clock stop mode configuration is undefined and cannot provide guaranteed operation. The McBSP is being used as the SPI master so I will configure CLKSTP/CLKXP/CLKRP as 1100b (as defined state per table 6-2) in the revision.

    I would like further clarification on CLKRM bit. I understand that signal is irrelevant since CKLSTP = 11b. However, I still wonder if the existing design (MCLKR pin configured as an output pin while also being driven from an unsynchronized external source) could possibly affect proper operation of McBSP internal chip hardware (noise interference, saturation of MOS gates, latch-up, etc..) and contribute to data receive errors. Note that the frame sync pin is also being driven from an external source. I intend to modify the configuration to define both of these pins as input pins (CLKRM=0 and FSRM=0) even though I don't use the signals. This is so that I do not need to change hardware boards in existing systems to remove external drive signals; simpler to download new firmware version to eliminate drive signal collision condition on these pins
  • 0 in reply to Lenio Cacula
    Guru 30330 points
    Lenio, please see my response in the other thread and use that one for other follow up questions. e2e.ti.com/.../2513407