CCS/F28M36P63C2: Illegal instruction trap

Part Number: F28M36P63C2

Tool/software: Code Composer Studio

Hello,

I am still looking for a solution to fix the above post. Any suggestion is welcome as i am unable to zero in on what i could be doing wrong.

Thank you,
Srini

Hello vamsi,

Thanks for your time. Would you please elaborate on how i can check these Flash ECC errors and do step execution as you mention?? This is what i see when i run the C28

and inserting breakpoints doesn't help as it halts at the very first line of code. 

Thanks,

Srini

Srini,

For ECC errors: Please look at 5.4.4 Control Subsystem Flash ECC/Error Log Registers in TRM.  Make sure ECC_ENABLE is enabled in your code (refer to InitFlash()).  When itrap occurs, check the SINGLE_ERR_ADDR and UNC_ERR_ADDR registers in the registers view.  

Single step: In CCS debug view, use the Step Over button (F6) available in top toolbar (see attached image) instead of resume button.  You can step through each function/instruction using this.  You can use Step Into button if you want to enter a function to step through it.  I will ask our analog experts to help you, since I see InitAdc1() as the last executed function.

Thanks and regards,

Vamsi  

Hello Vamsi,

I looked through my Initflash() function and i can confirm that i have enabled ECC. But when i look at that Register's contents in Register view, it reads 0x00000000. Also when the trap occurs, the contents of  SINGLE_ERR_ADDR and UNC_ERR_ADDR registers are also 0x00000000.  Please look at image below, i have highlighted the registers and the piece of code where i write 0xA into the ECC_ENABLE register.

And i stepped into my code line by line and the trap does occur in the InitAdc1(). and it occurs right after the highlighted line of code in the below image

Any suggestion on how i can fix this,

Thank you for your valuable time and assistance,

Srini

Vamsi,

This is my DELAY_US() function, as you can see i have it assigned to ramfuncs.

;//###########################################################################
;// TITLE: Simple delay function
;// DESCRIPTION:
;// This is a simple delay function that can be used to insert a specified
;// delay into code.
;// This function is only accurate if executed from internal zero-waitstate
;// SARAM. If it is executed from waitstate memory then the delay will be
;// longer then specified.
;// To use this function:
;//  1 - update the CPU clock speed in the F28M36x_Examples.h
;//    file. For example:
;//    #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
;//  2 - Call this function by using the DELAY_US(A) macro
;//    that is defined in the F28M36x_Device.h file.  This macro
;//    will convert the number of microseconds specified
;//    into a loop count for use with this function.
;//    This count will be based on the CPU frequency you specify.
;//  3 - For the most accurate delay
;//    - Execute this function in 0 waitstate RAM.
;//    - Disable interrupts before calling the function
;//      If you do not disable interrupts, then think of
;//      this as an "at least" delay function as the actual
;//      delay may be longer.
;//  The C assembly call from the DELAY_US(time) macro will
;//  look as follows:
;//  extern void Delay(long LoopCount);
;//        MOV   AL,#LowLoopCount
;//        MOV   AH,#HighLoopCount
;//        LCR   _Delay
;//  Or as follows (if count is less then 16-bits):
;//        MOV   ACC,#LoopCount
;//        LCR   _Delay
;//###########################################################################
;// $TI Release: F28M36x Support Library v206 $
;// $Release Date: Thu Mar  5 10:16:50 CST 2015 $
;// $Copyright: Copyright (C) 2012-2015 Texas Instruments Incorporated -
;//             http://www.ti.com/ ALL RIGHTS RESERVED $
;//###########################################################################

       .def _DSP28x_usDelay
       .sect "ramfuncs"

        .global  __DSP28x_usDelay
_DSP28x_usDelay:
        SUB    ACC,#1
        BF     _DSP28x_usDelay,GEQ    ;; Loop if ACC >= 0
        LRETR

;There is a 9/10 cycle overhead and each loop
;takes five cycles. The LoopCount is given by
;the following formula:
;  DELAY_CPU_CYCLES = 9 + 5*LoopCount
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
; The macro DELAY_US(A) performs this calculation for you
;
;

All the functions that i want to run from RAM are assigned to section "ramfuncs" in SysCtrl.c file

#pragma CODE_SECTION(InitFlash, "ramfuncs");
#pragma CODE_SECTION(SetupFlash, "ramfuncs");
#pragma CODE_SECTION(FlashGainPump,"ramfuncs");
#pragma CODE_SECTION(FlashLeavePump,"ramfuncs");

I made a few changes to my Linker cmd file, i no longer have the .TI.ramfunc in my linker .cmd file. Please see below,

/*
//###########################################################################
// FILE:    F28M36H63C2_generic_wshared_C28_FLASH.cmd
// TITLE:   Linker Command File For all F28M36x Devices
//###########################################################################
// $TI Release: F28M36x Driver Library vAlpha1 $
// $Release Date: February 27, 2012 $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
// The header linker files are found in <base>\F28M36x_headers\cmd
// For BIOS applications add:      F28M36x_Headers_BIOS.cmd
// For nonBIOS applications add:   F28M36x_Headers_nonBIOS.cmd
========================================================= */

/* Define the memory block start/length for the F28M36x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28M36x are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks or flash sectors can be
         be combined if required to create a larger memory block.
*/

MEMORY
{
PAGE 0:    /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   RAML1       : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   
   FLASHN      : origin = 0x100000, length = 0x002000     /* on-chip FLASH */
   FLASHM      : origin = 0x102000, length = 0x002000     /* on-chip FLASH */
   FLASHL      : origin = 0x104000, length = 0x002000     /* on-chip FLASH */
   FLASHK      : origin = 0x106000, length = 0x002000     /* on-chip FLASH */
   FLASHJ      : origin = 0x108000, length = 0x008000     /* on-chip FLASH */
   FLASHI      : origin = 0x110000, length = 0x008000     /* on-chip FLASH */
   FLASHH      : origin = 0x118000, length = 0x008000     /* on-chip FLASH */
   FLASHG      : origin = 0x120000, length = 0x008000     /* on-chip FLASH */
   FLASHF      : origin = 0x128000, length = 0x008000     /* on-chip FLASH */
   FLASHE       : origin = 0x130000, length = 0x008000      /* on-chip FLASH */
   FLASHD      : origin = 0x138000, length = 0x002000      /* on-chip FLASH */
   FLASHC      : origin = 0x13A000, length = 0x002000      /* on-chip FLASH */
   FLASHA      : origin = 0x13E000, length = 0x001F80      /* on-chip FLASH */
   
   CSM_RSVD    : origin = 0x13FF80, length = 0x000070     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x13FFF0, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   FLASH_EXE_ONLY_P0  : origin = 0x13FFF2, length = 0x000002  /* Part of FLASHA.  Flash execute only locations in FLASHA */ 
   ECSL_PWL_P0 : origin = 0x13FFF4, length = 0x000004     /* Part of FLASHA.  ECSL password locations in FLASHA */
   CSM_PWL_P0  : origin = 0x13FFF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD21A, length = 0x0006A0     /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FD8BA, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FE40A, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FE496, length = 0x0000AA     /* IQ Math Tables in Boot ROM */

   BOOTROM     : origin = 0x3FED6A, length = 0x001200     /* Boot ROM */
   PIEMISHNDLR : origin = 0x3FFFBE, length = 0x000002      /* part of boot ROM  */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */
   BOOT_RSVD   : origin = 0x000002, length = 0x00009F     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x0000A1, length = 0x00035F     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2       : origin = 0x00A000, length = 0x001000     /* on-chip RAM block L2 */
   RAML3       : origin = 0x00B000, length = 0x001000     /* on-chip RAM block L3 */

   CTOMRAM     : origin = 0x03F800, length = 0x000380     /* C28 to M3 Message RAM */
   MTOCRAM     : origin = 0x03FC00, length = 0x000380     /* M3 to C28 Message RAM */
   
   FLASHB      : origin = 0x13C000, length = 0x002000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/

SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA      PAGE = 0, ALIGN(4)
   .pinit              : > FLASHA,     PAGE = 0, ALIGN(4)
   .text               : > FLASHH      PAGE = 0, ALIGN(4)
   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         PAGE = 0, ALIGN(4)


   flashexeonly        : > FLASH_EXE_ONLY_P0 PAGE = 0, ALIGN(4)
   ecslpasswds         : > ECSL_PWL_P0 PAGE = 0, ALIGN(4)
   csmpasswds          : > CSM_PWL_P0  PAGE = 0, ALIGN(4)
   csm_rsvd            : > CSM_RSVD    PAGE = 0, ALIGN(4)
   
   /* The following section definitions are required when using the IPC API Drivers */ 
   GROUP : > CTOMRAM, PAGE = 1 
   {
       PUTBUFFER 
       PUTWRITEIDX 
       GETREADIDX 
   }

   GROUP : > MTOCRAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }   
   
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0       PAGE = 1
   .ebss               : > RAML2       PAGE = 1
   .esysmem            : > RAML2       PAGE = 1

   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA      PAGE = 0, ALIGN(4)
   .switch             : > FLASHA      PAGE = 0, ALIGN(4)

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA      PAGE = 0, ALIGN(4)            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
   DMARAML2           : > RAML2,       PAGE = 1
   DMARAML3           : > RAML3,       PAGE = 1
   SFRA_F_Data 			: > RAML2, 		PAGE = 1
   cntl_coeff_RAM 	: > RAML2, 	PAGE =1
   cntl_var_RAM 	: > RAML2, 	PAGE =1

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS     PAGE = 0, TYPE = DSECT

}

SECTIONS
{
	SINTBL							: > FLASHB				PAGE = 1
}
/*
*/

And this is the piece of code using the memcpy() function,

#ifdef _FLASH
// Copy time critical code and Flash setup code to RAM
// This includes the following functions:  InitFlash();
// The  RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart
// symbols are created by the linker. Refer to the device .cmd file.
    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);

// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
    InitFlash();
#endif

Thanks,

Srini

Vamsi,

The trap still occurs when the DELAY_US() function is called inside the InitAdc1(). And the ECC_ENABLE register still read 0x00000000. I double checked to see if all the functions are assigned to .TI.ramfunc()

Here's something i find peculiar, in the image below, do you think it's odd that the InitFlash() function is not highlighted in blue. For Ex, like the InitSysCtrl() function?

Thanks,
Srini