I'm trying to synchronize 4PWMs in HRPWM up-count mode. If I do not change the period, all 4 PWMs will be in sync, but if I change it when the PWMs are running the ePWM4 goes out of sync. The period and the duty cycle are correct but it will be phase shifted. If I enable the ePWM5 it will be in the same sync as ePWM4. Below is the initialization of the PWMs. I have added 32-bit access to period register.
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
EPwm1Regs.TBPRDM.all = FLOAT_TO_HRPWM(period);
EPwm1Regs.CMPA.all = FLOAT_TO_HRPWM(cmpa);
EPwm1Regs.TBPHS.bit.TBPHS = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Select up count mode
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm1Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // LOAD CMPA on CTR = 0
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.AQCTLA.all = 0;
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR; // PWM toggle high/low
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBRED.bit.DBRED = DEAD_TIME;
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable EPWMx_INT generation
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; // Enable event time-base counter equal to Zero
EPwm1Regs.ETPS.bit.INTCNT = 1; // ePWM Interrupt Event: 1 event has occurred.
EPwm1Regs.ETPS.bit.INTPRD = 1; // ePWM Interrupt: Generate an interrupt on the first event INTCNT = 01 (first event)
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
EPwm1Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
EPwm1Regs.TZSEL.all = 0; // Trip-Zone Submodule configuration
// Enable ePWM1 in PIE
PieCtrlRegs.PIEIER3.bit.INTx1 = 1; // Enable INT 3.1 in the PIE
IER |= M_INT3;
EDIS;
EPwm1Regs.AQCSFRC.bit.CSFA = 1; // Pull low at startup
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
EPwm2Regs.TBPRDM.all = FLOAT_TO_HRPWM(period);
EPwm2Regs.CMPA.all = FLOAT_TO_HRPWM(cmpa);
EPwm2Regs.TBPHS.bit.TBPHS = 2; // Compensation to delay (2*SYSCLKOUT) of the sync signal
EPwm2Regs.TBCTR = 0;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Select up count mode
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // TBCTR phase load on SYNC
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm2Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // LOAD CMPA on CTR = Period
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBRED.bit.DBRED = DEAD_TIME;
EPwm2Regs.AQCTLA.bit.PRD = AQ_SET; // PWM toggle high/low
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.EPWMXLINK.bit.TBPRDLINK = EPWMXLINK_EPWM1; // Link EPWM2 TBPRDM register to EPWM1 TBPRDM register
EPwm2Regs.EPWMXLINK.bit.CMPALINK = EPWMXLINK_EPWM1; // Link EPWM2 CMPA register to EPWM1 CMPA register
EALLOW;
EPwm2Regs.HRCNFG.all = 0x0;
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
EPwm2Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
EPwm2Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
EPwm2Regs.TZSEL.all = 0; // Trip-Zone Submodule configuration
EDIS;
EPwm2Regs.AQCSFRC.bit.CSFA = 1; // Pull low at startup
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
EPwm3Regs.TBPRDM.all = FLOAT_TO_HRPWM(period);
EPwm3Regs.CMPA.all = FLOAT_TO_HRPWM(cmpa);
EPwm3Regs.TBPHS.bit.TBPHS = 2;
EPwm3Regs.TBCTR = 0;
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Select up count mode
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm3Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // LOAD CMPA on CTR = 0
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.AQCTLA.all = 0;
EPwm3Regs.AQCTLA.bit.PRD = AQ_CLEAR; // PWM toggle high/low
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBRED.bit.DBRED = DEAD_TIME;
EALLOW;
EPwm3Regs.HRCNFG.all = 0x0;
EPwm3Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
EPwm3Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
EPwm3Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
EPwm3Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
EPwm3Regs.TZSEL.all = 0; // Trip-Zone Submodule configuration
EDIS;
EPwm3Regs.AQCSFRC.bit.CSFA = 1; // Pull low at startup
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
EPwm4Regs.TBPRDM.all = FLOAT_TO_HRPWM(period);
EPwm4Regs.CMPA.all = FLOAT_TO_HRPWM(cmpa);
EPwm4Regs.TBPHS.bit.TBPHS = 2; // Compensation to delay (2*SYSCLKOUT) of the sync signal
EPwm4Regs.TBCTR = 0;
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Select up count mode
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // TBCTR phase load on SYNC
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm4Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // LOAD CMPA on CTR = Period
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm4Regs.DBRED.bit.DBRED = DEAD_TIME;
EPwm4Regs.AQCTLA.bit.PRD = AQ_SET; // PWM toggle high/low
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.EPWMXLINK.bit.TBPRDLINK = EPWMXLINK_EPWM3; // Link EPWM4 TBPRDM register to EPWM3 TBPRDM register
EPwm4Regs.EPWMXLINK.bit.CMPALINK = EPWMXLINK_EPWM3; // Link EPWM4 CMPA register to EPWM3 CMPA register
EALLOW;
EPwm4Regs.HRCNFG.all = 0x0;
EPwm4Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
EPwm4Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for HR period
EPwm4Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
EPwm4Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control.
EPwm4Regs.TZSEL.all = 0; // Trip-Zone Submodule configuration
EDIS;
EPwm4Regs.AQCSFRC.bit.CSFA = 1; // Pull low at startup
Any ideas?
JHi
