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CCS/TMS320F28375D: CPU2 breaking at address "0x3FEC52" with No Debug Information available

Amtech
Genius 4575 points
Part Number: TMS320F28375D

Tool/software: Code Composer Studio

Hello,

I am using TMS320F28375D SOC, I have programmed it for dual CPU and when I run both the CPU simultaneously, CPU2 crashes with the message "Break at address "0x3FEC52" with no debug information available, or outside the program code." I have experimented and found that both CPU individually works fine when another CPU is on hold i.e CPU2 works fine when CPU1 is on hold and CPU1 works fine when CPU2 is on hold. But both CPU are not working simultaneously.

What could be the probable issue? Could it be (i) IPC (ii) Memory Configuration (iii) Initialization of Clocks or PIE, or it is something other?

Kindly help me with the same to identify and solve the problem. I am also attaching the screenshot of the error.

Thanks in Advance

Shubham

  • 0
    TI__Mastermind 32415 points
    Hi Shubham,

    It could be some timing related issue.
    Are you using any synchronization mechanism between the cores. I would recommend you do some IPC communication after the CPU1 does the system initialization, so that the CPU2 is on wait until the the clocks and other configurations are up. You could use the IPC_sync function for this purpose.


    Regards,
    Veena
  • 0 in reply to Veena Kamath
    TI__Mastermind 32415 points
    Hi,

    I just wanted to follow up with you. Were you able to resolve the issue?

    Regards,
    Veena
  • 0 in reply to Veena Kamath
    Genius 4575 points

    Hello Veena,

    Sorry, I couldn't reply, and yes I have solved the issue. I restarted with the initialization and there were multiple errors including timing issues and resetting of watchdog. But now its absolutely fine.

    Thanks a lot for your time and concern.

    Have a nice day.

    Regards,

    Shubham