LAUNCHXL-F28379D: SCI looping errors

I have SCI-B setup to transmit and receive FIFO I am using SCIA and C successfully with the same setup but B will not write from RXBUF to TXBUF.  I have these pin MUX and GMUXs and have linked those ports with a jumper wire:

EALLOW;

GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2;
    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2;
    GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0;
    GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 0;

EDIS;

The txbuf can be written to, but the RXBUF cannot receive that result and is stuck on a value assigned at initialization(76) these are my setup configs

Fifo 

void scib_fifo_init()
{   //initializes first in first out buffer for TX and RX
    ScibRegs.SCIFFTX.all = 0xE040;
    /*Bit 15 = 1:  SCI FIFO can resume transmit or receive. SCIRST should be 1 even for Autobaud logic to work.
    Bit 14 = 1: SCI FIFO enhancements are enabled
    Bit13 = 1:  Re-enable transmit FIFO operation
    Bit 12-8 = 0: FIFO is empty
    Bit 7 = 0: TXFIFO interrupt has not occurred, read-only bit
    Bit 6 = 1:  Write 0 has no effect on TXFIFINT flag bit, Bit reads back a zero
    Bit 5 = 0: TX FIFO interrupt based on TXFFIL match (less than or equal to) is disabled
    Bit 4-0 = 0: TXFFIL N/A
    */
    ScibRegs.SCIFFRX.all = 0x2044;
    /*Bit 15 = 0:    Receive FIFO has not overflowed, read-only bit
    Bit 14 = 0: Write 0 has no effect on RXFFOVF flag bit, Bit reads back a zero
    Bit13 = 1:   Re-enable receive FIFO operation
    Bit 12-8 = 0: FIFO is empty
    Bit 7 = 0: RXFIFO interrupt has not occurred, read-only bit
    Bit 6 = 1:   Write 1 to clear RXFFINT flag in bit 7
    Bit 5 = 0:  RX FIFO interrupt based on RXFFIL match (greater than or equal to) will be disabled
    Bit 4-0 = 0: RXFFIL N/A
    */
    ScibRegs.SCIFFCT.all = 0x0;
    /*Bit 15 = 0: Auto-baud detection is not complete. "A","a" character has not been received successfully.
    Bit 14 = 0:  Write 0 has no effect on ABD flag bit. Bit reads back a zero.
    Bit 13 = 0:   Disables auto-baud alignment
    Bit 12-8 = 0: Reserved
    Bit 7-0 = 0: FFTXDLY Reset set pause between character detections on the RX and TX FIFOs 0-> 0 baud delay
    */
    }

init