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TMS320F28375D: I2C - does I2CSTR.BB need slave device to pull down SCLK for it to get set?

Part Number: TMS320F28375D


Hello,

I had a working I2C code, but we've changed the board slightly and now it doesn't work.

I've noticed the busy bit doesn't get set by my write function.

It would help me a lot to know whether the BB bit in status register gets set solely by code setting I2CMDR.STT to 1 or if it only gets set after some slave device accepts the address specified in I2CSAR. Would you kindly clarify this to me?

Sorry for not appending code at this time.

Thank you,

Jiri

  • Hi Jiri,

    Below info is taken from the I2C TRM section:

    After a START condition and before a subsequent STOP condition, the I2C bus is considered busy, and
    the bus busy (BB) bit of I2CSTR is 1. Between a STOP condition and the next START condition, the bus
    is considered free, and BB is 0.

    I had a working I2C code, but we've changed the board slightly and now it doesn't work.

    If all you changed was hardware, I think it would hlep your debug to probe the SCL/SDA I2C lines to see the activity on the bus during writes / reads. Feel free to post screenshots of waveforms here.

    Best,

    Kevin

  • Hi Kevin,

    sorry for the delay. I think I figured it out. Due to a bug my code was holding SCLK low which prevented the controller from starting the transaction -> no BB.

    Thanks!

    Jiri