MSP430FR5969: Clarification of tSBW, En parameter in UART BSL

George Hug

Part Number: MSP430FR5969

There appears to be confusion about the length of the first positive pulse on TEST as part of the hardware BSL invocation sequence. In figure 2 of slau550p, it shows this as tSWB,En, and the datasheet shows a maximum of 110 uS for this parameter. But the text above Figure 2 says the pulse must be at least tSWB,En. The G2553 datasheet shows a maximum tSBW,En of 1 uS, but by actual measurement BSLDEMO outputs a 15 mS pulse. The source code for the Rocket is shown below. It appears to be trying to exactly match 110 uS, which doesn't tell me if it's treating that as a minimum or a maximum.

Can someone clarify if there is a minimum or maximum length for that pulse to work with ANY MSP430 part?
If it was 10 mS, would that work for everything?

/*** BSL entry sequence *******************************************************/

void BSL_invoke_sequence()
{
  /* BSL invoke sequence 
   *
   *       H -----------+     +--+  +-----+
   * TEST  L            +-----+  +--+     +--------
   *
   *       H --------------+           +-----------
   * RST   L               +-----------+
   *
   *
   *       H -----------------+  +--+     +--------
   * TCK   L                  +--+  +-----+
   */

  // Set RST, TST and TCK pin to output
  ENTRY_SEQ_PDIR |= (RESET_PIN + TEST_PIN + TCK_PIN);

  // (0)Start with RST high, TEST high, TCK high
  ENTRY_SEQ_POUT = RESET_PIN + TEST_PIN + TCK_PIN;
  __delay_cycles(INVOKE_DELAY_100US);
  __delay_cycles(INVOKE_DELAY_100US);

  // (1)RST high, TEST low, TCK high
  ENTRY_SEQ_POUT = RESET_PIN + TCK_PIN;
  __delay_cycles(INVOKE_DELAY_100US);

  // (2)RST low, TEST low, TCK high
  ENTRY_SEQ_POUT = TCK_PIN;
  __delay_cycles(INVOKE_DELAY_2US);

  // (3)RST low, TEST high, TCK low
  ENTRY_SEQ_POUT = TEST_PIN ;
  __delay_cycles(INVOKE_DELAY_110US);

  // (4)RST low, TEST low, TCK high
  ENTRY_SEQ_POUT = TCK_PIN;
  __delay_cycles(INVOKE_DELAY_10US);

  // (5)RST low, TEST high, TCK low
  ENTRY_SEQ_POUT =TEST_PIN;
  __delay_cycles(INVOKE_DELAY_100US);

  // (6)RST high, TEST high, TCK low
  ENTRY_SEQ_POUT = RESET_PIN + TEST_PIN;
  __delay_cycles(INVOKE_DELAY_100US);
  
  // (7)RST high, TEST low, TCK high
  ENTRY_SEQ_POUT = RESET_PIN + TCK_PIN;
  __delay_cycles(INVOKE_DELAY_100US);
  __delay_cycles(INVOKE_DELAY_100US);

  // Set RST, TST and TCK pin to input
  ENTRY_SEQ_PDIR &= ~(RESET_PIN + TEST_PIN + TCK_PIN);
}

over 7 years ago

0 Clemens Ladisch over 7 years ago

Guru 317000 points

The BSL has nothing to do with SBW.

Anyway, the G2553 datasheet says:

t_SBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾ max: 1µs

(1) Tools that access the Spy-Bi-Wire interface need to wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge.

So this maximum value describes the MSP chip itself, i.e., the emulation hardware needs at most this time to initialize. When it comes to how your programming tool should behave, you must use this value as a minimum.

0 zrno soli over 7 years ago

Guru 34483 points

This entry sequence with 100 / 110 us delay is related to FRAM devices only, as you already noticed it is few us in flash families. This is minimum value for FRAM entry sequence.

0 George Hug over 7 years ago in reply to Clemens Ladisch

Genius 4350 points

Thanks very much. So if I correctly understand what both of you are saying, the Maximum tSBW,EN value shown in the datasheets is the Minimum positive pulse duration for hardware BSL invocation. Is that right?. And is there a Maximum positive pulse width?

0 zrno soli over 7 years ago in reply to George Hug

Guru 34483 points

Yes. There are in slau320 EntrySequences_* functions where you can see typical delays used by TI. For example...

static void EntrySequences_RstHigh_JTAG()
{
    ClrTST();    //1
    MsDelay(4); // reset TEST logic

    SetRST();    //2
    
    SetTST();    //3
    MsDelay(20); // activate TEST logic

    // phase 1
    ClrRST();    //4
    usDelay(60);

    // phase 2 -> TEST pin to 0, no change on RST pin
    // for 4-wire JTAG clear Test pin
    ClrTST();  //5

    // phase 3
    usDelay(1);

    // phase 4 -> TEST pin to 1, no change on RST pin
    // for 4-wire JTAG
    SetTST();//7
    usDelay(60);

    // phase 5
    SetRST();
    MsDelay(5);
}

0 Clemens Ladisch over 7 years ago in reply to George Hug

Guru 317000 points

Yes. And there is no maximum specfified, so you can wait as long as you want.

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MSP430FR5969: Clarification of tSBW, En parameter in UART BSL