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DMA working control packet semantics

Andrew Schultz
Prodigy 140 points


Hello,

I was hoping someone could clear up some confusion around the DMA working control packet semantics.  From reading the TRM it says that the bits in the working control packet are "only updated after a channel is arbitrated out from the priority queue" and from the following post:

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/158061.aspx#578719

It seems that this means "these registers will not update until this channel is kicked out and another channel runs".  Based on testing, if I only have one DMA channel running and I try to poll the working packet registers, they seem to never update (which would make sense if this channel is never "aribrated away").  Am I understanding this correctly?  What I really want to be able to do is read CDADDR or CTCOUNT from the working control packet while my DMA is running to get its "progress".  From the interpretation I am getting, this seems impossible (short of "chaining" a bogus transaction on another channel).  Is this correct, or is there some way to do what I am trying to do.  Thanks.

  • 0
    TI__Mastermind 49120 points

    Andrew,

    The DMA control registers PBACSADDR, PBACDADDR, and PBACTC show the current source address, current destination address and current transfer count of the active channel. I believe this should help your application get the information necessary. If a DMA channel gets arbitrated out, then the information about the channel gets stored in the working control packet to support resumption from that point onwards. You can tell the number of pending and active DMA channels by reading the DMASTAT register.

    Regards, Sunil