Exception vector relocation?

Marco Moreno

Hi,

From my understanding of the CortexR4 on the TMS570, there is no real way to relocate the exception vector table during run-time to another location in flash. Is this correct? I read on another post that there is a V-bit in the CPU that would normally allow this, but the TMS570 would not be able to use this facility. In other words, will the CPU always reference this exception table at flash location zero?

        B       Reset
;undefEntry
        B       UndefinedException
;svcEntry
        B       SvcException
;prefetchEntry
        B       PrefetchException
;DataAbort
        B       DataException
;reservedEntry
        B       ReservedException
;IRQ
        ldr pc,[pc,#-0x1b0]
;FIQ
        ldr pc,[pc,#-0x1b0]

This does not pose a problem for the IRQ and FIQ, since those instructions reference the VIM registers which would have to be setup later in the application.  However, for the other exceptions this causes an issue.  I have a small bootloader program that is capable of jumping to two different applications that are located in separate flash areas.  I would like for each application to have its own implementation of these exception handlers, but I don't see a way to do this at the moment without maybe adding some markers in RAM to steer the bootloader exceptions to the proper application exceptions.

Can someone confirm this and/or suggest alternatives?

Thanks,

Marco

over 13 years ago

0 KGreb over 13 years ago

TI__Mastermind 23000 points

Hello,

The ARM Cortex R architecture only allows the interrupt vectors to be located at one of two locations -- 0x0 or 0xFFFF0000. Because the high vector address is in legacy peripheral space (not flash or SRAM space), we have disallowed use of the high vector address. Please note that ARM has already deprecated or removed the high vector address feature on other Cortex A/R cores.

However, we are able to provide some additional flexibility. It is possible to swap the SRAM and the flash address space chip selects via the system module. This configuration requires that a CPU reset be generated for the CPU to re-read the configuration. Once this is done you have the possibility to have your base vectors in volatile SRAM.

Regards,

Karl

0 Anja Visnikar over 12 years ago in reply to KGreb

Prodigy 90 points

Hello!

I have a project that is used for testing purposes and should be based in RAM without any writes to FLASH, if possible. I can initialize register values before running the program, so I could write to necessary registers to swap them beforehand. I would like to use the vector table located at 0x08000000.

Can you please elaborate on this option that you mentioned - swapping the SRAM and FLASH address space chip selects?

Thank you very much,
Anja

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Exception vector relocation?