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MibSPI RAM Access during Transfer Group being active

Pashan None
Genius 5660 points

Hello Support,

What is the side-effect of accessing/modifying Transfer RAM of MibSPI in Muti-Buffer Mode belonging to a currently non-active Transfer Group when a particular Transfer Group is active sending data over SPI at a paricular instant of time?

Is it a requirement that CPU/DMA should not access/modify Transfer RAM of MibSPI in any way when any of the available Transfer Group is active transferring data using SPI Bus? or it doesn't not matter as long as the active Transfer RAM is untocuhed by CPU/DMA.

Any info will help me a lot to understand Transfer Group activity.

Thank you.

Regards

Pashan

 

  • 0
    TI__Genius 13810 points

    This is a advanced question. I will forward your question to our SPI expert.

    Regards,

    Haixiao

  • 0 in reply to Haixiao Weng
    TI__Genius 14205 points

    Hi Pashan

    Internally, MIBSPI will read a TXRAM location whenever it’s supposed to transfer a data.

    At the end of a transfer, the RX data will be copied to the RXRAM. Typically, the arbitration scheme is,

    1. If both VBUSP( User write) access and MIBSPI FSM( Module ) access Mib RAM at the same time, then FSM will take priority
    2. If either of them is already accessing, then the other access will wait.

    There are two possibilities.

    1. When FSM tries to access MibRAM, if a VBUSP port is already accessing the RAM, then

    FSM access will be stalled till VBUSP access completes.

    1. Similarly, if FSM is already accessing MIbRAM while VBUSP port tries to access the RAM, it will have to wait.

    Overall, there should not be any functional issues. But, the # of cycles might vary if there are a lot of VBUSP accesses to MibRAM during Transfer Group transactions.

    Best Regards
    Prathap