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TMS570 nTRST for JTAG

Brent Shen
Intellectual 335 points

Hi there,

The datasheet indicates that there is an internal pull-down resistor on the nTRST pin of TMS570 for JTAG purpose. Since this pin is active low, why does it have a pull-down resistor instead of a pull-up resistor? On my circuit, I connected the nTRST pin to 3.3V through an external pull-up resistor (10kohm). Is this connection wrong? If so, could you recommend the proper usage of the nTRST pin? Thank you.

Regards,

Brent Shen

  • 0
    Intellectual 335 points

    Hi there,

    The reason why I posted the info above is because I'm having power-on issue with TMS570(...20216). Basically, the code downloaded into TMS570 doesn't run at all. Luckily, below is the reason of power-on failure.

    1)      I found out that nTSRT of TMS570 should be logic low during normal operation mode of TMS570, whereas logic high during code download/debug mode through JTAG interface.

    2)      However, the TMS570 datasheet appears to be a little confusing, by indicating that nTSRT is an active low signal without specifying in which of the two circumstances above.

    3)      As a result, on my board, I connected this pin to 3.3V through an external pull-up resistor of 10kohm. When TMS570 is powered on, this pin remains logic high and TMS570 enters the debug mode automatically (which is not desired in my application). In such a case, no code downloaded previously into TMS570 can run normally while nError pin of TMS570 remains logic high (meaning no error generated from the ESM module).

    Maybe it's just me. With all my respect, please put some detailed comment for nTRST pin in your datasheet to avoid unnecessary confusion. Thank you.

    Regards,

    Brent Shen

  • 0 in reply to Brent Shen
    TI__Guru 59540 points

    Hi Brent,

    Although I can certainly appreciate your concern and confusion on this topic, the polarity of the pin as tied to its function determines the active state designation. i.e., this pin is intended to drive the JTAG test logic into reset. As such, this pin is active low meaning that the JTAG/debug logic is in reset (inactive debug session but active reset signal to the logic) when the pin is driven low and out of reset when driven high (active debug session with the inactive reset signal to the logic). This is why there is an internal pull down on the pin so this signal is maintained in it's active state during application runtime.

    Hopefully, this explanation makes it more clear why this pin is labeled the way it is and improves the understanding of how to connect the nTRST pin. For further examples, schematics for our HDKs are located on the TI website.

    http://processors.wiki.ti.com/index.php/TMS570_MDK_Kit