How to make SDRAM work in Hercules HDK

Michael

The VCLK3 is directly used to feed EMIF clk. For EMIF clk frequency, pls refer the datasheet (pls tell me part number I can look it up for you as well), the max. frequency on RM48Lx30 is 66.7MHz. You want to reduce the VCLK3 to this value.

The EMIF clk is by default gated, hopefully you have enabled that as well. PINMUX29[8] is cleared to ungate this clock

At a quick glance, other settings do look correct, so pls chk if this fixes your problem.

Hey Abhishek,

Thank you for your quick reply. Unfortunately it leaves me a little more confused :-(

I am using the Hercules HDK from Texas Instruments. It is equipped with a RM48L950AZWIT controller and SDRAM IS42S16400F-7BL.
According the the datasheet for the SDRAM it can run on 200MHz. (I have tried other speeds but without success!)
I am using HALCodGen version: 03.03.00

My confusion comes with the CLK-gate signal!

I cannot find the PINMUX29[8] in HALCodGen, but found on top of the PINXMUX-fane: "Gate off EMIF_CLK output". I have tried to check it and the board works a little different now. At random I can now change the content of a SDRAM-cell, but it is not consistent. That could be some fine-tuning of timing-signals!

But, I looked through the reference-manual for RM48, spnu503.pdf (September, 2012), and searched for "GATE CLK". This led me to GPREG1. In chapter 4.3.3, 2nd bullet it says that "Any application that requires EMIF functionality must set GPREF1[31]".
Though in chapter 10.6.5, bit 31 of GPREG1 is marked reserved and write has no effect!!!!

Please help me:
* Is it the correct pin that I have checked in HALCodGen?
* Shall I set bit 31 of GPREG1?
* Do you have a sample project that uses the SDRAM of the Hercules SDK?

I will in the meantime try to tune the timing parameters for the SDRAM to see if it changes to the better :-)

Thank you for your help.

Best regards
    Michael c".)

Hello again,

I have tried to lower the VCLK3 to 100MHz and that made the SDRAM work after I checked the "Gate off EMIF_CLK output" :-)

Why  does the flag need to be checked when I have specified that I will use EMIF?

Still, I am confused about the GPREG1[31] and I do appreciate your comment on it.
In the software I have running now, I do not touch this register. I have searched through all the code made by HALCodGen, and the GPREG1 is not touched!

Thanks a lot for the help!

Best regards

    Michael c".)

Michael

CHecking the "Gate off EMIF_CLK output" is causing the clock to be ungated. This behavior is unfortunately contradictory. I will fan this issue out.

GPREG[31] does need to be set. HALCOGEN doesn't set it, you have to set this manually. Can you tell what is the value you observe at 0xFFFF_FFA0 (GPREG1)?

It is possible that the signal values are such that they give the appearance of SDRAM working correctly even with this bit cleared, but pls make sure this bit is set for correct operation.

Hello Abhishek,

If I do not set bit 31 in GPREG1, I read 0x0005FFFF from GPREG1.

If I do set bit 31 in GPREG1, I read 0x8005FFFF from GPREG1.

I cannot see any difference in the behaviour of the SDRAM in the two cases!!!!

It seems a little spooky to me!!!

Best regards
   Michael c".)

Dear Michael Enggaard Pedersen ,

pls let us know the step by step to make SDRAM working on RM48 HDK ..

Hello,

I will try to specify the steps:

1. Select the correct VCLK3 that matches the capabilities of your processor
    We used the table: "Table 4-31. EMIF Synchronous Memory Switching Characteristics" to select VCLK3

2. On the PinMux page in HalCoGen, check Gate Off EMIF_CLK output

3. Fill in the values for the SDRAM you are using, and enable SDRAM on the EMIF General page.

4. Generate the code with HalCoGen

5. In the file sys_startup.c, just before the to __cmain, insert:
systemREG1->GPREG1 |= 1u << 31;

6. In the same file insert the call to emif_SDRAMInit

7. Insert in the sys_link.cmd the SDRAM as needed.
   For our purpose the following line was modified:
   define region RAM     = mem:[from 0x08001500 size 0x0003EB00];
   to
   define region RAM     = mem:[from 0x08001500 size 0x0003EB00] | mem:[from 0x80000000 size 0x00800000];

7. Compile and run ! :-)

This is as far as I can see from our code what we do.

Please, if you find find improvements to it, please post it here to make to procedure complete and working!

Best regards

   Michael c".)