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Masking CAN Messages

Alexandr Lyalko
Prodigy 50 points
Other Parts Discussed in Thread: HALCOGEN, TMS570LS3137

Hello,

I got a problems with using mask on CAN messages on TMS570LS3137. Any mask that I'm trying to apply pass any messages that I'm sent. CAN interface configured by HalCoGen 3.03.01. using of CAN mask is necessary in my project.

Here are codes of using and initialization: 

void canTRFunc()
{
while(1)

{
canTransmit(canREG1, canMESSAGE_BOX1, canTX);

while(!canIsRxMessageArrived(canREG2, canMESSAGE_BOX1));

canGetData(canREG2, canMESSAGE_BOX1, canRX);

sciDisplayText(scilinREG, "RECEIVED: ", sizeof("RECEIVED: "));
sciDisplayText(scilinREG, canRX, sizeof(canRX));
sciDisplayText(scilinREG, txtCRLF, sizeof(txtCRLF));

}
} 

 void canInit(void)
{
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** @b Initialize @b CAN1: */

/** - Setup control register
* - Disable automatic wakeup on bus activity
* - Local power down mode disabled
* - Disable DMA request lines
* - Enable global Interrupt Line 0 and 1
* - Disable debug mode
* - Release from software reset
* - Enable/Disable parity or ECC
* - Enable/Disable auto bus on timer
* - Setup message completion before entering debug state
* - Setup normal operation mode
* - Request write access to the configuration registers
* - Setup automatic retransmission of messages
* - Disable error interrupts
* - Disable status interrupts
* - Enter initialization mode
*/
canREG1->CTL = 0x00000000U
| 0x00000000U
| 0x00000005U
| 0x00020043U;

/** - Clear all pending error flags and reset current status */
canREG1->ES = canREG1->ES;

/** - Assign interrupt level for messages */
canREG1->INTMUXx[0U] = 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U;

canREG1->INTMUXx[1U] = 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U;

/** - Setup auto bus on timer period */
canREG1->ABOTR = 0U;

/** - Initialize message 1
* - Wait until IF1 is ready for use
* - Set message mask
* - Set message control word
* - Set message arbitration
* - Set IF1 control byte
* - Set IF1 message number
*/
while (canREG1->IF1STAT & 0x80);

canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);
canREG1->IF1ARB = 0x80000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);
canREG1->IF1MCTL = 0x00001080U | 0x00000C00U | 1U;
canREG1->IF1CMD = 0xF8;
canREG1->IF1NO = 1;

/** - Setup IF1 for data transmission
* - Wait until IF1 is ready for use
* - Set IF1 control byte
*/
while (canREG1->IF1STAT & 0x80);

canREG1->IF1CMD = 0x87;

/** - Setup IF2 for reading data
* - Wait until IF1 is ready for use
* - Set IF1 control byte
*/
while (canREG1->IF2STAT & 0x80);

canREG1->IF2CMD = 0x17;
/** - Setup bit timing
* - Setup baud rate prescaler extension
* - Setup TSeg2
* - Setup TSeg1
* - Setup sample jump width
* - Setup baud rate prescaler
*/
canREG1->BTR = (0U << 16U) |
((2U - 1U) << 12U) |
(((3U + 2U) - 1U) << 8U) |
((2U - 1U) << 6U) |
19U;

/** - CAN1 Port output values */
canREG1->TIOC = (1 << 18 )
| (0 << 17 )
| (1 << 3 )
| (0 << 2 )
| (0 << 1 )
| (0 );
canREG1->RIOC = (1 << 18 )
| (0 << 17 )
| (1 << 3 )
| (0 << 2 )
| (0 <<1 )
| (0 );


/** - Leave configuration and initialization mode */
canREG1->CTL &= ~0x00000041U;


/** @b Initialize @b CAN2: */

/** - Setup control register
* - Disable automatic wakeup on bus activity
* - Local power down mode disabled
* - Disable DMA request lines
* - Enable global Interrupt Line 0 and 1
* - Disable debug mode
* - Release from software reset
* - Enable/Disable parity or ECC
* - Enable/Disable auto bus on timer
* - Setup message completion before entering debug state
* - Setup normal operation mode
* - Request write access to the configuration registers
* - Setup automatic retransmission of messages
* - Disable error interrupts
* - Disable status interrupts
* - Enter initialization mode
*/
canREG2->CTL = 0x00000000U
| 0x00000000U
| 0x00000005U
| 0x00020043U;

/** - Clear all pending error flags and reset current status */
canREG2->ES = canREG2->ES;


/** - Assign interrupt level for messages */
canREG2->INTMUXx[0U] = 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U;

canREG2->INTMUXx[1U] = 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U
| 0x00000000U;


/** - Setup auto bus on timer period */
canREG2->ABOTR = 0U;

/** - Initialize message 1
* - Wait until IF1 is ready for use
* - Set message mask
* - Set message control word
* - Set message arbitration
* - Set IF1 control byte
* - Set IF1 message number
*/
while (canREG2->IF1STAT & 0x80);

canREG2->IF1MSK = 0xC0000000U | ((0x00000000U & 0x1FFFFFFFU) << 0U);
canREG2->IF1ARB = 0x80000000U | 0x40000000U | 0x00000000U | ((1U & 0x1FFFFFFFU) << 0U);
canREG2->IF1MCTL = 0x00001080U | 0x00000400U | 1U;
canREG2->IF1CMD = 0xF8;
canREG2->IF1NO = 1;

/** - Setup IF1 for data transmission
* - Wait until IF1 is ready for use
* - Set IF1 control byte
*/
while (canREG2->IF1STAT & 0x80);

canREG2->IF1CMD = 0x87;

/** - Setup IF2 for reading data
* - Wait until IF1 is ready for use
* - Set IF1 control byte
*/
while (canREG2->IF2STAT & 0x80);

canREG2->IF2CMD = 0x17;
/** - Setup bit timing
* - Setup baud rate prescaler extension
* - Setup TSeg2
* - Setup TSeg1
* - Setup sample jump width
* - Setup baud rate prescaler
*/
canREG2->BTR = (0U << 16U) |
((2U - 1U) << 12U) |
(((3U + 2U) - 1U) << 8U) |
((2U - 1U) << 6U) |
19U;

/** - CAN2 Port output values */
canREG2->TIOC = (1 << 18 )
| (0 << 17 )
| (1 << 3 )
| (0 << 2 )
| (0 << 1 )
| (0 );
canREG2->RIOC = (1 << 18 )
| (0 << 17 )
| (1 << 3 )
| (0 << 2 )
| (0 <<1 )
| (0 );

/** - Leave configuration and initialization mode */
canREG2->CTL &= ~0x00000041U;


/** @note This function has to be called before the driver can be used.\n
* This function has to be executed in privileged mode.\n
*/

/* USER CODE BEGIN (4) */
/* USER CODE END */
}

Regards, Alexandr.

  • 0
    TI__Mastermind 22715 points

    Alexandr,

    I have passed your question to HALCoGen team. They will provide an answer to you shortly.

    Thanks and regards,

    Zhaohong

  • 0
    TI__Expert 7650 points

    Hello Alexandr,

    We have received your post.  One of our experts will get back to you shortly.

  • 0 in reply to Brian Fortman
    TI__Intellectual 1235 points

    Hi Alexandr,

        IMHO, you set the MASK for standard ID to be 0x000 and enabled MASK function by UMASK bit in IF1MCTL register.

        This means, the target Mbox will accept all the standard IDs, since "0" in mask bits = "don't care".

        If you would like to configure the mask to "only a few IDs may pass", you need more "1"s in the mask bits.

        Is that what caused your problem?

        

        

  • 0 in reply to Renton Ma
    Prodigy 50 points

    Hello Renton,

    I tried to apply different mask values, but result did not change. Besides, regardless of the mask value, I can not use different MESSAGE_BOXes to transmit from CAN1 and receive on CAN2 (if I use MESSAGE_BOX1 to transmit from CAN1, I can receive massage on CAN2 with using only MESSAGE_BOX1). 

    Regards, Alexandr

     

  • 0 in reply to Alexandr Lyalko
    TI__Intellectual 1235 points

    Hi Alexandr,

        Could you please try setting the mask bit to be 0x7FF first?

        This shall block all other IDs except for the one you set via the IF1ARB interface.

        Also, by checking your code, I think you did not set any specific ID to the Mbox of either DCAN1 or DCAN2, right?

        (they remain the default values by HALCoGen of 0x01.)

        I would recommend to set a specific ID for testing, say 0x501 (to be sent by DCAN1).

        On DCAN2 side, set the Mbox1 with ID of 0x500.

        By doing this first  with 0x7FF as mask (on DCAN2, Mbox1), your DCAN2 shall not be able to receive the message sent by DCAN1 with ID of 0x501.

        If this is the result,  try set the mask to 0x7FE.

        This will make the DCAN2 able to receive the message.

       (As you mentioned for "always Mbox1 reception", I assume that is caused by the priority of Mboxes.

        If 2 or more Mboxes of a DCAN module are able to response to a single message ID, the priority is always to the Mbox with the lowest number.

        And that in your case, Mbox1 response to the message always...I suppose...)

  • 0 in reply to Renton Ma
    Prodigy 50 points

    Hi Renton,

    Thank you very much for the expert help. Problem is successfully solved.

    Thanks and Regards, Alexandr

     

     

  • 0 in reply to Alexandr Lyalko
    TI__Intellectual 1235 points

    Hi Alexandr,

        You are welcome.

        Glad to know it helped :)

    Best regards.

    Ma