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Stuck-at-fault by STC

Nomo
Guru 16800 points


Hi,

In page 346 (8.4.10) of TRM (spnu499), "Insert stuck-at-fault inside CPU so that STC signature compare will fail" is described.
I want to know what the fault is inserted, how the fault is inserted, where the fault is inserted and what happened by insertion of the fault, I must discuss it whether it is safety or not with my customers.
Could you explain the flow from the insertion of the fault to the detection of it?

Thanks

Nomoto

  • 0
    TI__Genius 9015 points

    Hello Nomoto,

    I have forwarded your question to the expert on this.  They will be responding soon.

  • 0 in reply to John Hall
    TI__Intellectual 1480 points

    Hello nemoto,

    The stuck-At fault is applied to the data path between the output of the Self test  controllers psuedo ramdom pattern generator which feeds in as an primary input to the CPU.

    This is acheived through to enabling combinatorial logic  which emulates an stuck-At fault when the SELF_CHECK_KEY is configured to 1010 and the Fault_INS bit is configured to 1 in the STCSCSCR register.

    Hercules forum support

  • 0 in reply to Hari Pendurty
    Guru 16800 points

    Hello Hari,

    Thank you for your reply.
    Is the Stuck-At fault applied to the data path at the output of the Self test controllers pseudo random pattern generator?
    Or, is the fault applied to the data path between the output of the Self test controllers and pseudo random pattern generator?
    I don't know the Self test controllers pseudo random pattern generator.
    And I think the pseudo random pattern generator is for DFT, so if Stuck-At fault applied to DFT, it is not fault in normal mode, I think.
    Could you teach me where the Stuck-At fault applied concretely?

    If Stuck-At fault is applied somewhere, what modules work to detect the fault?
    CCM, COMP BLK1 in FSM and so on.

    I want to know the detailed flow of the fault handling.
     
    Thanks

    Nomoto

  • 0 in reply to Nomo
    TI__Intellectual 1480 points

    Hello Nomoto,

    Please find my answers embedded below
    Is the Stuck-At fault applied to the data path at the output of the Self test controllers pseudo random pattern generator?
    Or, is the fault applied to the data path between the output of the Self test controllers and pseudo random pattern generator?

    Hari >> It is applied to the data path at the output of the Self test controllers pseudo random pattern generator. So you can assume that a fault is emulated at the Primary input of the CPU.


    I don't know the Self test controllers pseudo random pattern generator.
    And I think the pseudo random pattern generator is for DFT, so if Stuck-At fault applied to DFT, it is not fault in normal mode, I think.
    Could you teach me where the Stuck-At fault applied concretely?

    Hari >>  The pseudo random pattern generator(PRPG)  is a part of the functional logic of the  self test controller(STC) .In functional mode(self test mode in this case) the PRPG is not a DFT but a functional component/element. That is why to cover latent fault detects for Self test we implemented the stuck at  logic at the output of the PRPG which is an primary input to the CPU in self test mode with this implementation you get the best coverage for the data path from the self test controller to the CPU and back to self test controller which check for the current signature of the test.

    Hercules forum support