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Possible ways Cortex-R4 can perform Speculative Access beyond APPLICATION Definition

Pashan None
Genius 5660 points
Other Parts Discussed in Thread: TMS570LS0432

Hello Support,

In the following e2e link it is mentioned that under certain circumstances Cortex-R4 can perform SPECULATIVE DATA as well as INSTRUCTION PREFETCH beyond the Address ranges defined by the APPLICATION Image.
Can you please provide me with some idea about the ways these things can happen within the Sane APPLICATION CODE?

http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/228184/802204.aspx#802204

Thank you.
Regards
Pashan

  • 0
    TI__Mastermind 23000 points

    Hello Pashan,

    The simplest case to consider is when linear prefetch exceeds past the end of defined application code.  On this and many other processors with prefetch capability, it can be a best practice to pad the end of code in a defined application with a few NOP instructions, such that valid (if non-functional) code is fetched before a branch or other discontinuity at the end of the application code is processed.

    If we consider branch prediction, then another case is possible as the R4 will speculate on branch target for indirect branches.  ARM describes this case in the R4 TRM, DDI0363G, section 5.2.

    Regards,
    Karl 

  • 0 in reply to KGreb
    Genius 5660 points

    Hello Karl,

    From your description I am understanding that SPECULATIVE FETCH occurs only for Instruction Prefetch.

    There is no SPECULATIVE FETCH for Data Prefetch.

    Is my understanding correct?
    Please confirm.

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Mastermind 22715 points

    Pashan,

    There is also speculative fetch for data read. If a LDR instruction is prefetched, the data will be also be prefetched.

    A common example is that the last instruction of an interrupt service routine is "subs". CPU does not consider this instruction as the end of the function. It will keep fetching. If there is function placed next to the ISR and there is a LDR in the beginning, The LDR instruction and the data will be prefetched. Since the address pointer for the LDR instruction is not set yet, this speculative data fetch can go anywhere. 

    In the attached example, a GIO_Dummy() function is placed next to GIO_ISR. We can generate a speculative data fetch on a known address to test the memory system.

    0640.gio_test_spec.c

    To summarize, speculative fetch is a Cortex-R4 feature to ease the memory access bottleneck. Speculative instruction prefetch will always occur in the memory defined by your application. Speculative data prefetch could occur outside the memory defined by your application. A user should define all accessible memory in the application to avoid undesired behavior. Speculative fetch is only applicable to "normal" memory type.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 5660 points

    Hello Zhaohong,

    Thank you for the detailed example. I will try to recreate the example Speculative Data Fetch with your code.

    "Since the address pointer for the LDR instruction is not set yet, this speculative data fetch can go anywhere. "

    From the above statement of yours, I am assuming Speculative Fetch can be anywhere within 4GB [32-Bit] address space and not constraint by the avaliable TCM Size [Address Range] for the particular device.
    Is that correct? Please confirm.

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Mastermind 22715 points

    Pashan,

    From CPU perspective, speculative fetch could occur to anywhere in the "normal" memory (defined by R4 MPU) within the 32 bit address space. If you want to use the code I attached earlier, do not enable any optimization in compilation.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 5660 points

    Hello Zhaohong,

    So when Cortex-R4 CPU performs Speculative Fetch Access within "NORMAL" type memory [ Default Memory MAP in MPU according to DDI0363G ARM TRM  ] and the memory is physically unavailable within the specific DEVICE [e.g. TMS570LS0432 Corona], then also there will be no ABORT from TCM Interface to CPU.

    Is that correct?
    Please confirm.
    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Mastermind 22715 points

    Pashan,

    Your understanding is correct.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    TI__Mastermind 23000 points

    Two slight clarifications:

    1) The CPU core will assume all 4GB of address range are valid, except for special memory ranges such as the TCM where there is the possibility to limit address range (on binary boundaries which are pre-decoded inside the core).  The core expects that the error indication will come from slave logic which receives the transaction.  For a TCM access, such error would need to come from the relevant memory wrapper.  For AXI-M access, this would come from either the level two interconnect or the level three interconnect (PCR).

    2) While the CPU may only prefetch an instruction from NORMAL memory, data requested by that instruction need not be in a NORMAL region.

    Regards,
    Karl