I use TMS570LS20216 MDK. In the Flexray demo code, I see that the SIR register is cleared in the transmit_check_node_a(FRAY_ST *Fray_PST) before checking the CYCS bit for cycle start. When the cycle start happens at Fr_StartCommunication(FRAY_ST *Fray_PST), why SIR register is cleared and checked every time?
In ILE Register, Interrupt Line CC_int1 is enabled and CC_int0 is disabled. When all interrupts related to ERAY_int0 are cleared and checked, why 0x2 is passed to this register instead of 0x01?
