Hello,
let me to describe simlified HW. We have external device eating data stream. It has HW line signalizing that next data can be sent (empty buffer signal). And we would like to use this signal as DMA request.
Here is setting for DMA channel (for Halcogen generated driver)
g_dmaCTRL dmaCtl0 = {
(U32) dmaTxBuf, //uint32 SADD; /* Initial source address */
0x60000000u, //uint32 DADD; /* Initial destination address */
0, //uint32 CHCTRL; /* Next channel to be triggered + 1 */
32, //uint32 FRCNT; /* Frame count */
2, //uint32 ELCNT; /* Element count */
0, //uint32 ELDOFFSET; /* Element destination offset */
1, //uint32 ELSOFFSET; /* Element source offset */
0, //uint32 FRDOFFSET; /* Frame destination offset */
1, //uint32 FRSOFFSET; /* Frame source offset */
2, //uint32 PORTASGN; /* DMA port */
3, //uint32 RDSIZE; /* Read element size */
3, //uint32 WRSIZE; /* Write element size */
0, //uint32 TTYPE; /* Trigger type - frame/block */
1, //uint32 ADDMODERD; /* Addressing mode for source */
0, //uint32 ADDMODEWR; /* Addressing mode for destination */
0 //uint32 AUTOINIT; /* Auto-init mode */
};
............. to start DMA:
dmaReqAssign(0, 39);
dmaSetPriority(0, LOWPRIORITY);
dmaSetCtrlPacket(0, dmaCtl0);
dmaSetChEnable(0, DMA_HW);
It works, but there is problem. We are set that active level for DMA reqest channel is "1". But HW has different behavior. When this line is active before DMA channel setting, transfer will not start.
Can you describe this behavior better? Is DMA request driven by level as is described in TRM SPNU563 chapter 20.3.1.91 DMA Request Polarity Select Register 1 (DMAREQPS1). Or DMA transfer is activated by 0->1 event on external pin?
Now, if external signal is active before DMA setting we are able to start transfer only with one aditional "dmaSetChEnable(0, DMA_SW)" command. And we don't use it because here is race condition problem. This additional SW start can be duplicate to HW and to trigger unwanted transfer.
Have a nice day,
Jiri
