Dual clock comparator

Hi Livo,

First of all the DCC module is not meant to detect jitters in the test clock if this is the question you are asking.

It will depends on the VALID window you configure. Note that the minimum VALID value will be 4 according to the TRM. So the accuracy of the VCLK will be 4 VCLK cycles from the reference clock. Please refer to the VALID register in the TRM.

Hi Livo,
Here is one application note about DCC where you will find it helpful to answer further DCC questions.

www.ti.com/.../spna211.pdf

Hi Charles
Thanks for the replay.
In the example reported in the spna211 (for me it is not a good example because PLL is monitored with the OSCIN source so that if there is a OSCIN drift also the PLL will drift) the PLL frequency is checked with an accurancy of 0.1%.
Using HFLPO as reference source and VCLK as clock under test can I obtain the same accurancy??
and if it is not possible, how much is it the minimun accurancy settable??

Regards
Livio Franchin

Livio,

The most accurate frequencies in your system are the oscillator and then the PLL. The LPO is not tightly controlled. I would not know how to characterize the accuracy.

This is a little bit like trying to measure microns with a meter stick. The LPO has more variability than the clock you want to measure.

Best Regards,

Kevin Lavery