EMIF Time Gap between consecutive Read/Write Operation

Hello Nestor,

 Is the CPU accessing the EMIF in strongly-ordered memory mode? If you could change to 'Device' I think you could get some performance improvement?

 In HalcoGen go to the R4-MPU-PMU tab and look for the MPU region corresponds to the EMIF. The EMIF Async memory starts at 0x60000000. In the memory type the default selection is STRONGLYORDERED_SHAREABLE. Please change to DEVICE_SHAREABLE. See below. Make the change and see if it improves.

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Hello Charles，

Thank your answer. I try it following your description，but  it  has only 3 clks short. Do you have other  method?

Hi Nestor,
Ok, so it does help a bit. I don't think there is much to improve. When you first do a read, the data needs to travel from the EMIF module and the internal interconnect before arriving at the CPU's pipeline. If the write data depends on the read data then the CPU can not write to the EMIF until it finishes reading. it can take quite some cycles to read from the EMIF to the CPU's pipeline. It takes similar number of cycles for the CPU to write to the EMIF module. This has a direct relationship with the gap you see on the EMIF interface before the write data comes out.

Hi Charles,

Yes, it helps. We also tried consecutive write-write, I believe there is no need to wait for the previous data write to be successful when the next data is sent. But the time gap is still considered too long.

Does TI have any documents that describe the EMIF data path and the time it takes for reads/writes？

Nestor,

Try accessing an 8byte quantity (uint64_t or uint32_t). I found that EMIF does kind of a "burst" mode that converts the 64 bit access to 4x16 bit access (if you are using 16-bit wide mode else 8x8?) with the "minimum" gap between strobes.

If you have consecutive address in your FPGA, you can use this "feature" to squeeze some cycles out. If you try a 32bit access you get 2 bursts. And as Charles mentioned, mpu device mode gets the minimum gap.

Hi TI experts,

My concern is Does TI have any documents that describe the EMIF data path and the time it takes for reads/writes？

Our setting is 90MHz for EMIF clock, we would like to know therotically how high can our read/write operation frequecy go? now we can reach about 3MHz. We would like to know if there is any room for improvement?

Nestor,

We don't have any throughput data for this part. You can try using the DMA instead of the CPU if you need to move large blocks of data.
It should have less latency than the CPU and give you better throughput.