Hello,
I have used the SafeTI library initialization code to initialize the TMS570LS1115 MCU. It is working properly. But I would like to be sure that the SafeTI based initialization covers all the aspects of the initialization sequence described in application note SPNA106D (Initialization of Hercules™ ARM® Cortex™-R4F
Microcontrollers)
I crosschecked the HALCoGen generated sys_startup.c, SaftTI example startup code and the application note.
In the application note section 2, there are 57 initialization steps.
1. I could not find the FPU enable function in either HALCoGen generated code or SafeTI example code. How to enable FPU?
2. The application note points 3, 4 and 5 are handled in the HALCoGen generated code through following function calls.
_coreEnableEventBusExport_(); flashWREG->FEDACCTRL1 = 0x000A060AU; _coreEnableFlashEcc_();
But I cannot see that code in SafeTI example code. Do we need to combine this code with SafeTI example code?
3. The step 22 of initialization application note talks about LBIST on CPU. I believe this is achieved by calling
pbistSelfCheck();
But this is not available in SafeTI code. How to perform this test?
4. In the HALCoGen code., before running PBIST tests on ESRAM following function is called to Disable RAM ECC.
_coreDisableRamEcc_();
But it is not called in the SafeTI example? Is this internally handled by the SafeTI library?
5. Following errata function is not called in SafeTI example. Do we need that errata function
errata_PBIST_4();
6. Initialization steps 34,35 and 36 talks about memory auto initialization and checking parity error detection mechanism for peripherals. This is implemented in the HALCoGen sys_startup.c code.
It calls number of xxxxParityCheck() functions for different peripherals. But this is not done in SafeTI example. In this case do I need to use this code in combination with the SafeTI code for proper operation? (I have copied the code below
mibspiREG1->GCR0 = 0x1U;
/* Release the MibSPI3 modules from local reset.
* This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
*/
mibspiREG3->GCR0 = 0x1U;
/* Release the MibSPI5 modules from local reset.
* This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
*/
mibspiREG5->GCR0 = 0x1U;
/* USER CODE BEGIN (56) */
/* USER CODE END */
/* Enable parity on selected RAMs */
enableParity();
/* Initialize all on-chip SRAMs except for MibSPIx RAMs
* The MibSPIx modules have their own auto-initialization mechanism which is triggered
* as soon as the modules are brought out of local reset.
*/
/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
*/
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
memoryInit( (uint32)((uint32)1U << 1U) /* DMA RAM */
| (uint32)((uint32)1U << 2U) /* VIM RAM */
| (uint32)((uint32)1U << 5U) /* CAN1 RAM */
| (uint32)((uint32)1U << 6U) /* CAN2 RAM */
| (uint32)((uint32)1U << 10U) /* CAN3 RAM */
| (uint32)((uint32)1U << 8U) /* ADC1 RAM */
| (uint32)((uint32)1U << 14U) /* ADC2 RAM */
| (uint32)((uint32)1U << 3U) /* HET1 RAM */
| (uint32)((uint32)1U << 4U) /* HTU1 RAM */
| (uint32)((uint32)1U << 15U) /* HET2 RAM */
| (uint32)((uint32)1U << 16U) /* HTU2 RAM */
);
/* Disable parity */
disableParity();
/* Test the parity protection mechanism for peripheral RAMs
NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
/* USER CODE BEGIN (57) */
/* USER CODE END */
het1ParityCheck();
/* USER CODE BEGIN (58) */
/* USER CODE END */
htu1ParityCheck();
/* USER CODE BEGIN (59) */
/* USER CODE END */
het2ParityCheck();
/* USER CODE BEGIN (60) */
/* USER CODE END */
htu2ParityCheck();
/* USER CODE BEGIN (61) */
/* USER CODE END */
adc1ParityCheck();
/* USER CODE BEGIN (62) */
/* USER CODE END */
adc2ParityCheck();
/* USER CODE BEGIN (63) */
/* USER CODE END */
can1ParityCheck();
/* USER CODE BEGIN (64) */
/* USER CODE END */
can2ParityCheck();
/* USER CODE BEGIN (65) */
/* USER CODE END */
can3ParityCheck();
/* USER CODE BEGIN (66) */
/* USER CODE END */
vimParityCheck();
/* USER CODE BEGIN (67) */
/* USER CODE END */
dmaParityCheck();
/* USER CODE BEGIN (68) */
/* USER CODE END */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
/* wait for MibSPI1 RAM to complete initialization */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
/* wait for MibSPI3 RAM to complete initialization */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
/* wait for MibSPI5 RAM to complete initialization */
/* USER CODE BEGIN (69) */
/* USER CODE END */
mibspi1ParityCheck();
/* USER CODE BEGIN (70) */
/* USER CODE END */
mibspi3ParityCheck();
/* USER CODE BEGIN (71) */
/* USER CODE END */
mibspi5ParityCheck();
7. After the 44th initialization step, the rest of the steps are not available in either of the codes.
(ie. HALCoGen and SafeTI) Therefore please instruct on how to perform 44 - 54 initialization steps. They are not described in the application note.
I know the question is lengthy. But I would like to know for sure that I am doing this properly since the application demands proper safety.
Thank you
