About Livelock of SRAM

Haggy

I'm reading the "Safety Manual for TMS570LS31x and TMS570LS21x Hercules ™ ARM®-Based Safety (SPNU511D)".

Please tell me about "7.104 Primary SRAM Hard Error Cache and Livelock".

For the test, If the user is possible to cause any Livelock?

When that became the state of Livelock, Do CPU is able to normal operation?

over 8 years ago

0 Anthony F. Seely over 8 years ago

TI__Guru 68920 points

I am not sure why you want to generate a Livelock but there are two conditions listed that could create a livelock.
You should be able to create one of these if you want to:

* Two single bit errors in a 64-bit unaligned 32-bit Thumb-2 instruction fetch
• A single bit error in a load instruction (LDR or LDM) followed by a single bit error in the instruction's data payload

But these are very specific cases to create.

0 Arriy over 8 years ago in reply to Anthony F. Seely

Expert 1720 points

Hi,Anthony.
Thank you your answer.

I want know how to occur single bit errors in Instruction.

0 Arriy over 8 years ago in reply to Arriy

Expert 1720 points

I want to answer this question.

Please answer.

0 Bob Crosby over 8 years ago in reply to Arriy

TI__Guru 72500 points

If using the linker to generate the ECC see section 8.4.12 of the ARM ALT User's Guide

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About Livelock of SRAM