Hello,
I would like some clarification about low power mode. Indeed, the entry condition is not very clear. The SPNU563 (section 2.4.3.1) give a sequence to enter in low power mode but the 4th step seems to be optional.
I understood from the TRM that only a Wait For Interrupt could trigger the low power mode in case of the CDDIS register bit 0 is set. Could you confirm that point ?
My concern about this point is that in the errata list of the TMS570LC4357 revB, a DMA transfer stopped by a low power mode will be wrong. My problem is that I will not be able to stop easily the DMA transfer in my system thus I would like to prevent to enter in low power mode.
Furthermore, I would like to get explanation about the sys module global low power request. For instance, in the DMA chapter of the TRM about power management (section 20.2.11), a paragraph said :
"When the system module issues a global low power request, the DMA will respond to the system modufle with an acknowledge as soon as an arbitration boundary is reached"
How the global low power request (and by the way the acknowledgement) works ? Is it only the clock gating ?
Thanks you.
Antoine
