Hello!
DCC#24 states that "Implication(s) The cycle count captured may be incorrect" with a workaround:
"Workaround(s) Static frequency offset can be removed by making two measurements and subtracting. The sporadic offset can be removed by making multiple measurements and discarding outliers -- an odd filtering algorithm"
Document Hercules PLL Advisory SSWF021#45 Workaround uses single shot mode in function check_frequency(). Is this verified to be working? I don't see multiple measurements being taken in the check_frequency() function, unless I am mistaken.
static uint32 check_frequency(uint32 cnt1_clksrc)
{
/* Setup DCC1 */
/* DCC1 Global Control register configuration */
dccREG1->GCTRL = (uint32)0x5U | /** Disable DCC1 */
(uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */
(uint32)((uint32)0xAU << 8U) | /** Single Shot mode */
(uint32)((uint32)0x5U << 12U); /** No Done Interrupt */
/* Clear ERR and DONE bits */
dccREG1->STAT = 3U;
/** DCC1 Clock0 Counter Seed value configuration */
dccREG1->CNT0SEED = 68U;
/** DCC1 Clock0 Valid Counter Seed value configuration */
dccREG1->VALID0SEED = 4U;
/** DCC1 Clock1 Counter Seed value configuration */
dccREG1->CNT1SEED = 972U;
/** DCC1 Clock1 Source 1 Select */
dccREG1->CNT1CLKSRC = (uint32)((uint32)10U << 12U) | /** DCC Enable/Disable Key */
(uint32)cnt1_clksrc; /** DCC1 Clock Source 1 */
dccREG1->CNT0CLKSRC = (uint32)DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */
/** DCC1 Global Control register configuration */
dccREG1->GCTRL = (uint32)0xAU | /** Enable DCC1 */
(uint32)((uint32)0x5U << 4U) | /** No Error Interrupt */
(uint32)((uint32)0xAU << 8U) | /** Single Shot mode */
(uint32)((uint32)0x5U << 12U); /** No Done Interrupt */
while (dccREG1->STAT == 0U)
{
/* Wait */
}
return (dccREG1->STAT & 0x01U);
}
Please clarify this issue for me.
Thanks!
Supporting documents:
