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TMS570LC4357: Cortex-R5 Core Fatal Bus Error on ESM for TMS570LC43x causing nError pin to become active

Swapnil Patel
Intellectual 635 points

Part Number: TMS570LC4357

Hi,

when my system boots up I am getting Cortex-R5 Core Fatal Bus Error (Group 2 channel 3 from the datasheet)  and which is causing my nError pin to become active. 

When I get the error, ESM register are

Stat2  = 0x00000008

 ErrPinStat  = 0x00000000

IntOffstHgh = 0x00000024

I am getting the error when my TI_Fee_init() function accesses Fee_BlockConfiguration[u16LoopIndex].FeeBlockNumber (where u16LoopIndex is 5).

I also get the error when I access Fee_BlockConfiguration memory block using memory browser. 

So it seems like accessing memory address 0x00074d80 is resulting in the the error that I am getting. 

But other that that, my application is running fine. But I need nError pin to work fine in order to implement TPS65381 nError pin monitoring for safety purposes. 

I have tried solutions mentioned in previous threads regarding this error with no success. 

I am using code composer studio 6.1.2 with Compiler TI v16.9.4. LTS 

on my Flash settings under Debug, Auto ECC Generation and Align program segments to 64-bit memory regions is checked off. and I am using "verify" for Flash verification settings.

Any help regarding this would be appreciated! 

Thanks,

 Swapnil 

  • 0
    Intellectual 635 points

    Solved it by following the procedure described here.

    Used palign instead of align in linker command file. 

    SECTIONS
{
    .intvecs : {} > VECTORS
    /* FreeRTOS Kernel in protected region of Flash */
    .kernelTEXT  palign(32) : {} > KERNEL
    .cinit       palign(32) : {} > KERNEL
    .pinit       palign(32) : {} > KERNEL
    /* Rest of code to user mode flash region */
    .text        palign(32) : {} > FLASH0 | FLASH1
    .const       palign(32) : {} > FLASH0 | FLASH1
    /* FreeRTOS Kernel data in protected regi	on of RAM */
    .kernelBSS    : {} > KRAM
    .kernelHEAP   : {} > RAM
    .bss          : {} > RAM
    .data         : {} > RAM    
    .sysmem       : {} > RAM
    FEE_TEXT_SECTION palign(32) : {} > FLASH0 | FLASH1
    FEE_CONST_SECTION palign(32): {} > FLASH0 | FLASH1
    FEE_DATA_SECTION : {} > RAM

/* USER CODE BEGIN (4) */
    .sysmem		  : {} > RAM
/* USER CODE END */
}

  • 0 in reply to Swapnil Patel
    TI__Guru 59540 points
    Swapnil:

    Thanks for posting the solution. I am glad you were able to leverage prior E2E materials to find the conclusion.