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TMS570LC4357: lwIP Problem: Unable to read PHY registers using MDIO interface

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi,

I am working on Hercules TMS570LC43x Development Kit. Trying to get the lwIP demo working.

According to the guidelines in the demonstration page ( processors.wiki.ti.com/.../HALCoGen_Ethernet_Driver_and_lwIP_Integration_Demonstration ), I have configured HalcoGEN project according to TMS570LC43x instructions.

After generating the code from HalcoGEN, I used the lwIP source and examples given in the demo archieve.

I also enabled the DIP switch on the board for enabling ethernet.

After compilig the application and loading it to the board, the application hangs on HL_mdio.c, MDIOPhyRegRead function at the following lines:

while((HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO) == MDIO_USERACCESS0_GO)
{ 
} /* Wait */

The baseAddr information is as follows:

Name : baseAddr
    Default:4244080896
    Hex:0xFCF78900

The following is the screenshot for the register information on MDIO_USERACCESS0:



I have looked up tens of threads within the forum for similar problems, but couldn't achieve to solve this problem.

What might the the problem?

HalcoGEN version: 04.06.00

Code Composer Studio version: 7.3.0.00019


Thanks,
Erkan

  • Hello Erkan,

    In HALCoGen pinmux, please check the column of "Alternate Terminal". The "Default Terminal" is for Launchpad, and the "Alternate Terminal" is for HDK.
  • Hi,

    As I've mentioned in my post, I've applied all the instructions for the demo project (I guess you are mentioning bullet 6 below). Is there any other part I should change?

    For TMS570LC43x and RM57x devices:
    
    1. Under the ‘Driver Enable’ tab, enable EMAC Driver and SCI1 Driver.
    2. Under ‘VIM RAM’ add the names of the ISRs for EMAC Transmit and Receive Interrupts (Channels 77 and 79 respectively).
    3. Enable these interrupts under the ‘VIM Channel 64-95’ tab.
    4. Under the ‘PLL’ tab, change the multiplier for both PLLs to a value of 150, such that the output frequency in both cases is 300.00 MHz.
    5. Under the ‘GCM’ tab, change the value of the VCLK1, VCLK2 and VCLK3 Dividers to 1 and VCLKA4 Divider to 2, such that the output of VCLKA4_DIV is 37.50 MHz.
    6. Under the ‘PINMUX’ tab, enable RMII/MII, under Pin Muxing. Under Input Muxing, enable MDIO(G3), MII_COL(F3), MII_CRS(B4), MII_RX_DV(B11), MII_RX_ER(N19), MII_RXCLK(K19), MII_RXD[0], MII_RXD[1], MII_RXD[2], MII_RXD[3], MII_TX_CLK.
    7. Under the ‘EMAC’ tab, change the EMAC address to the correct address (the default one in the example is mentioned above). The physical address is 1 by default.
    8. Generate the system initialization and HAL Code.

    Thanks,

    Erkan

  • Any response? I still have the problem.
  • Ok, I have found the issue to be the missing Pin Muxing instructions. Please update the demonstration page for the missing instructions.

    Under Pin Muxing tab, MDIO and MDCLK should be selected as follows:

  • Thanks Erkan for update.

    On Pin Muxing page, checking "MII" will select G3 for MDIO and V5 for MDCLK.
  • No, it does not, not in HalcoGEN v04.06.00 anyway.

    Also, I came across this information in one of your videos (training.ti.com/hercules-how-tutorial-ethernet)

    "The next step is to navigate to the PINMUX tab. We need to assign the pin functionality to MII module. Then we scroll down to the pin G3, and select MDIO. And then to the v5 pin and select MD clock. The PINMUX selection is now complete. "

    Can you check if it is a bug in HalcoGEN. If not, can you please add this information to the demonstration page.

    Thanks,
    Erkan
  • I've checked with HalcoGEN v04.07.00 and checking MII in PINMUX does not enable G3-MDIO and V5-MDCLK pins.

    Please either fix the bug in HalcoGEN (if it is a bug), or update the instructions on the HalcoGEN lwIP demo page.
  • Hello Erkan,

    I double checked the PINMUX in HACoGen 4.07. After MII is checked, the G3-MDIO and V5-MDCLK are selected too. Thanks