TMS570LS0332: ADC Sampling trigger based in RTI_COMP0

Hello Sreekanth,

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

Dear QJ Wang,

Thanks for your feedback. I have one more question. I tried by commenting out the following line to diable the RTI compare 0 interrupt signal to CPU.

rtiEnableNotification(rtiNOTIFICATION_COMPARE0);

The CPU RTI compare 0 interrupt is not triggering. At the same time, the ADC sampling is also not getting triggered. Is it possible to disable the signalling oof RTI compare 0 interrupt to CPU ?? (At the same time it should be signal the ADC).

Thanks & Best regards,
Sreekanth challa

Dear Sir/Madam,

Can you please provide your comments on this? I would like to have ADC sampled with RTI Compare 0 without microcontroller interrupt getting triggered.

Thanks & Best regards,

Sreekanth challa

Dear QJ Wang,

As you specified, i now use the following line of code in software and disable the RTI interrupt to CPU: Vim channel 02.
rtiEnableNotification(rtiNOTIFICATION_COMPARE0);

I still do not get the ADC sampling working. Are there any other configurations i should be doing?

Thanks & Best regards,
Sreekanth challa

Sreekanth,

ADC gets triggered by either a rising edge or a falling edge (default) on the RTI compare interrupt line output from the RTI module.

Here are the steps to get the RTI compare 0 interrupt to trigger the ADC:

• You need to enable the RTI compare 0 interrupt to be sent out of the RTI module. This causes a rising edge on the compare 0 interrupt line when the compare match event occurs.
• If you don't want to service this compare interrupt with the CPU, then disable the RTI compare 0 interrupt in the VIM. This means that the compare 0 interrupt will not be sent to the CPU
• The RTI module has a feature that allows you to clear the compare interrupt line automatically, without the CPU having to do this. This creates the falling edge on the RTI Compare interrupt line. This feture is documented in the TRM as well. The control register is called "Compare Interrupt Clear Enable Register" and is at address 0xFFFFFCAC. There is one enable for each of the four compare interrupt lines. There is a Compare 0 Clear Register (0xFFFFFCB0) that needs to be programmed to hold the compare value at which the interrupt line is cleared. The value in this register is automatically incremented by the value programmed in the Update Compare Register.
• This mechanism allows you to create a programmable PWM signal on the RTI Compare interrupt line, so that you can trigger the ADC with the period that you want.

Note that this feature is not supported by HALCoGen, so you will need to write your own routine to program the two registers to create the PWM for triggering the ADC.

Regards,

Sunil

Dear Sunil,

Thanks a lot for the prompt response. I have update the specified registers in rtiInit function. The controller is SYS mode. So this should be fine.

rtiREG1->INTCLRENABLE = (rtiREG1->INTCLRENABLE ^ 0x0FU);
rtiREG1->COMP0CLR = 500U;

I could see that COMP0CLR value is getting automatically incremented by the value un update compare register. I do not the ADC interrupt. I am using ADC group 1 and it is configure to generate the interrut upon completing the specified number of samples (i.e., threshold interrupt).

Thanks & Best regards,
Sreekanth challa

Sreekanth,

Can you please upload your adcInit() routine? If you are generating periodic triggers to the ADC, why would you generate an interrupt on a threshold number of conversion values? The conversion group being triggered should be in a single-conversion sequence mode with all results read out upon a "group conversion end" interrupt and then the next RTI trigger should occur.

Regards,
Sunil

Dear Sunil,

Please find the attached file (adc.c). I have added 2 functions (adcInit and adcEnableNotification functions) from HalCoGen generated file. Te main aim is to configure the adc event group channels once every RTI compare 0 interrupt. But trigger interrupt only once adc event threshold counter counts down to zero .

The ADC event group has 2 channels selected and FIFO size is configured to 20.  I have RTI Compare 0 configured to 50 uSec. The ADC captures 2 samples once every 50 uSec. With 500 uSec,  20 samples are completed.  ADC Event group interrupt triggers.

This works perfectly fine for me when i have RTI Compare 0 interrupt is enabled in VIM of HalCoGen.

Thanks & Best regards,

Sreekanth challa3324.adc.c

What are the values of the following registers in the ADC when the interrupt does not happen?

offset = 0x40 ADEVTHRINTCR
offset = 0x34 ADEVINTFLG
offset = 0x6C ADEVSR
offset = 0x88 ADSMSTATE
offset = 0x174 ADEVRAMWRADDR

Alternatively, you can take a snapshot of the ADC register frame in the debugger with the CPU halted and upload it.

Dear Sunil,

The following are the values of above requested address values-

offset = 0x40 ADEVTHRINTCR -> 0x00000014
offset = 0x34 ADEVINTFLG -> 0x00000004
offset = 0x6C ADEVSR -> 0x00000008
offset = 0x88 ADSMSTATE -> 0x00000000
offset = 0x174 ADEVRAMWRADDR -> 0x00000000

Thanks & Best regards,
Sreekanth challa

2311.MibADC Registers.txtDear Sunil,

Please find the exported register values of MibADC from CCS.

Thanks & Best regards,

Sreekanth challa

Sreekanth,

This indicates that the ADC is done with all pending conversions, and all conversion results have been read out. It is now waiting for the next trigger. Do you read the conversion results outside of the interrupt service routine or within the service routine?

Dear Sunil,

I do read the converted in samples in the task. I just post a semaphore in ISR indicating that samples are avilable. I will also stop the ADC conversion in ISR using the following function so that buffer will not over run.

adcStopConversion(adcREG1, group);

I believe that ADC event group is not sampling the channels. This is because the RTI Comapare 0 interrupt is not notified to ADC. As i said before ADC event group. The RTI Compare 0 is configured to 50 uSec. The RTI compare registers are configure to the following in rtiInit function.

/** - Setup compare 0 value. This value is compared with selected free running counter. */
rtiREG1->CMP[0U].COMPx = 500U;

/** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */
rtiREG1->CMP[0U].UDCPx = 500U;

As per your recommendations, i have the following lines to allow DMA to clear the interrupt flag to free the CPU. I write the following registers.

rtiREG1->INTCLRENABLE = (rtiREG1->INTCLRENABLE ^ 0x0FU);
rtiREG1->COMP0CLR = 500U;

Thanks & Best regards,
Sreekanth challa

Sreekanth,

There is a single counter that is compared for the set and clear operations for the flag. Your compare value for the clear needs to be (compare value for flag to be set + 500) so that the operation goes like this:

Counter value      Compare interrupt Flag

0                            Clear

500                        Set

1000                      Clear

1500                      Set

2000                      Clear

...

You may need to change the numbers if you need a faster trigger from the RTI.

Dear sunil,

As per your comments i have updated the the values as follows. Do not see any ADC complete interrupt.

rtiREG1->INTCLRENABLE = (rtiREG1->INTCLRENABLE ^ 0x0FU);
rtiREG1->COMP0CLR = 1000U;



The complete RTI init function is as shown below.

void rtiInit(void)
{
/* USER CODE BEGIN (3) */
rtiREG1->INTCLRENABLE = (rtiREG1->INTCLRENABLE ^ 0x0FU);
rtiREG1->COMP0CLR = 1000U;
/* USER CODE END */
/** @b Initialize @b RTI1: */

/** - Setup debug options and disable both counter blocks */
rtiREG1->GCTRL = 0x00000000U;

/** - Enable/Disable capture event sources for both counter blocks */
rtiREG1->CAPCTRL = 0U | 0U;

/** - Setup input source compare 0-3 */
rtiREG1->COMPCTRL = 0x00001000U | 0x00000100U | 0x00000000U | 0x00000000U;

/** - Reset up counter 0 */
rtiREG1->CNT[0U].UCx = 0x00000000U;

/** - Reset free running counter 0 */
rtiREG1->CNT[0U].FRCx = 0x00000000U;

/** - Setup up counter 0 compare value
* - 0x00000000: Divide by 2^32
* - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1)
*/
rtiREG1->CNT[0U].CPUCx = 15U;

/** - Reset up counter 1 */
rtiREG1->CNT[1U].UCx = 0x00000000U;

/** - Reset free running counter 1 */
rtiREG1->CNT[1U].FRCx = 0x00000000U;

/** - Setup up counter 1 compare value
* - 0x00000000: Divide by 2^32
* - 0x00000001-0xFFFFFFFF: Divide by (CPUC1 + 1)
*/
rtiREG1->CNT[1U].CPUCx = 7U;

/** - Setup compare 0 value. This value is compared with selected free running counter. */
rtiREG1->CMP[0U].COMPx = 500U;

/** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */
rtiREG1->CMP[0U].UDCPx = 500U;

/** - Setup compare 1 value. This value is compared with selected free running counter. */
rtiREG1->CMP[1U].COMPx = 5000U;

/** - Setup update compare 1 value. This value is added to the compare 1 value on each compare match. */
rtiREG1->CMP[1U].UDCPx = 5000U;

/** - Setup compare 2 value. This value is compared with selected free running counter. */
rtiREG1->CMP[2U].COMPx = 20000U;

/** - Setup update compare 2 value. This value is added to the compare 2 value on each compare match. */
rtiREG1->CMP[2U].UDCPx = 20000U;

/** - Setup compare 3 value. This value is compared with selected free running counter. */
rtiREG1->CMP[3U].COMPx = 20000U;

/** - Setup update compare 3 value. This value is added to the compare 3 value on each compare match. */
rtiREG1->CMP[3U].UDCPx = 20000U;

/** - Clear all pending interrupts */
rtiREG1->INTFLAG = 0x0007000FU;

/** - Disable all interrupts */
rtiREG1->CLEARINTENA = 0x00070F0FU;

/** @note This function has to be called before the driver can be used.\n
* This function has to be executed in privileged mode.\n
* This function does not start the counters.
*/

/* USER CODE BEGIN (4) */
/* USER CODE END */
}

Thanks ^ Best regards,
Sreekanth challa