TMS570LS0432: TMS570 ECC detection check

Hello TI team,

I know that there are a lot of topics on forum connected to ECC, but unfortunately I was not able to find answer on some my question and hope for your help.

Within out application we want to check periodically if SECDED triggered or not for both RAM and Flash in case of single bit error.

Without interrupts, without address retrieving (currently), just check, was single bit upset or not since previous check.

Here I want to provide my ideas how to do it, based on TRM, application notes and code from HalCoGen etc.

First of all if I want to check if ECC 1 bit error triggered I perform the following TCRAM1/2 configuration:

ECC_DETECT_EN = 0xA

RAMOCCUR = 0

RAMTHRESHOLD = 1

RAMINTCTRL.SERR_EN = 1

Question 1: Is defined above configuration complete and correct to monitor SECDED triggering (1 bit) for for BTCM?

Monitoring itself I done in the following way (register names a bit different but recognizable, I think; code is for TCRAM1 only, for TCRAM2 anther register is used and anther ESM channel):

/* Check if SECDED triggered within TCRAM1 (B0TCM) during the last frame */
if ((TcRam1Regs_g.RAMERRSTATUS.Bit.lSERR EQU (uint32_t)1U) OR
    ((uint32_t)((EsmRegs_g.lESMSR1 >> (uint32_t)SHIFT_26_BITS_C) & (uint32_t)1U) EQU (uint32_t)1U))
{

    /* SECDED triggered during the last frame for B0TCM */
    ...

    /* Clear RAMOCUUR in order to count subsequent single-bit error corrections */
    TcRam1Regs_g.RAMOCCUR.Bit.lSEO = (uint32_t)0U;

    /* Clear SERR flag */
    TcRam1Regs_g.RAMERRSTATUS.Bit.lSERR = (uint32_t)1U;

    /* Clear ESM Group 1 Channel 26 flag */
    EsmRegs_g.lESMSR1 |= (uint32_t)((uint32_t)1U << (uint32_t)SHIFT_26_BITS_C);
}

Question 2: Please confirm that ECC (1 bit error event) is catchable with the code above and handling is correct.

Question 3: Also am I right that during next call of the code above we able to catch new a 1bit error occurrence (if appear for sure :))?

Question 4: Do I need to read error address to catch the next error event or do some other handling?

Now let's continue with Flash check. Here is more complicated since I have a feeling that there is some typos in the TRM.

First of all to monitor 1 bit error I have configure wrapper as follows:

FEDACCTRL1.EDACEN = 0xA

FEDACCTRL1.EOFEN = 1

FEDACCTRL1.EZFEN = 1

FEDACCTRL1.EDACMODE = 0xA

Question 5: Please confirm that defined above configuration is complete and correct for 1bit error monitoring (check if event occurred or not, one or million times, doesn't matter)?

Now here is event occurrence check code itself:

if ((FlashRegs_g.FEDACSTATUS.Bit.lERR_ZERO_FLG EQU (uint32_t)1U) OR
    (FlashRegs_g.FEDACSTATUS.Bit.lERR_ONE_FLG EQU (uint32_t)1U) OR
    (FlashRegs_g.FEDACSTATUS.Bit.lB2_COR_ERR EQU (uint32_t)1U) OR
    ((uint32_t)((EsmRegs_g.lESMSR1 >> (uint32_t)SHIFT_6_BITS_C) & (uint32_t)1U) EQU (uint32_t)1U))
{
    /* SECDED triggered during the last frame for ATCM */
    ...

    /* Clear single-bit error flag(s) */
    FlashRegs_g.FEDACSTATUS.Bit.lERR_ZERO_FLG = (uint32_t)1U;
    FlashRegs_g.FEDACSTATUS.Bit.lERR_ONE_FLG  = (uint32_t)1U;
    FlashRegs_g.FEDACSTATUS.Bit.lB2_COR_ERR   = (uint32_t)1U;

    /* Clear ESM Group 1 Channel 6 flag */
    EsmRegs_g.lESMSR1 = (uint32_t)1U << SHIFT_6_BITS_C;
}

Question 6: Please confirm that code above is sufficient to check if 1 bit error event occurred or not?

Question 7: Also am I right that during next call of the code above we able to catch new a 1bit error occurrence?

Question 8: Do I need to read error address to catch the next error event or do some other handling?

Question 9: By TRM for me it is not completely clear why description of ERR_ONE_FLG is applicable for Bus2 only.

I thought that for Bus1 events like "wherea 1 readas a 0" are also applicable, isn't it?

ERR_ZERO_FLG is applicable for both Bus1 and Bus2 in accordance with TRM. What is the truth regarding these two regs?

Question 10: Do I need to check B2_COR_ERR or is it excess? What is other indicator (except ESM) that ECC error occurred on Bus2?

Question 11: If ERR_ONE_FLG and/or ERR_ZERO_FLG are set due to error on Bus1 data, will B2_COR_ERR be triggered?

I know there are a lot of question, but I think this information will be useful not only for me, cause I see that there are a lot of questions regarding ECC.

Thanks a lot in advance!