Original question:
Hello Vishal,
When the MCU's memory system cannot complete a memory access successfully, an abort is generated. Aborts can occur for a number of reasons, for example:
• a permission fault indicated by the MPU (memory protection unit)
• an error detected in the data by the ECC checking logic.
An error occurring on an instruction fetch generates a prefetch abort. Errors occurring on data accesses generate data aborts.
When a Prefetch Abort occurs, the processor marks the prefetched instruction as invalid, but does not take the exception until the instruction is to be executed. The processor reports the status and address of faults that occur during its operation. For both data and instruction faults there are two Fault Status Registers (FSRs) and one Fault Address Register (FAR).
Please read the value of those registers from CCS registers window to figure what instruction causes the PABT.
