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TMS570LS3137: Infinite loop details

sreenivasan m
Genius 3705 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi Team,

In ccmSelfCheck method and in other methods during startup self test, there are few places where there exist infinite while loops.
What is the maximum limit one has to wait in the while loop? 

Also, is there a way to get details on what the method does explicitly,  especially those written in assembly language?
Is Halcogen generated code is certified code? We are interested in understanding on how to tweak the coding standards in the generated code from Halcogen.

Also, the generated is very specific to the one configured in Halcogen GUI interface. Is there any way to generate the code generically and it can be configured as per user during run time?

Regards,
M.Sreenivasan.

  • 0
    TI__Guru**** 197336 points
    Hello Sreenivasan,

    There are 3 infinite for(;;) loops in selftest file. The code enters for(;;) loop when the self test of STC, PBIST, and CPU fails. The most while() loops in selftest file are used to check the status, for example to wait till test is completed. It doesn't take many cycles for those waiting loop, but you can add timeout to the while() loop.

    The code generated from HALCoGen is not certified. But the code development processing is certified. The HALCoGen Compliance Support Package (CSP) was developed to provide the necessary documentation, reports and unit test capability to assist customers using HALCoGen generated software to comply with functional safety standards such as IEC 61508 and ISO 26262.
  • 0 in reply to QJ Wang
    Genius 3705 points
    Thanks, can you provide us the details on how much time we have to wait in specific?. Also, the halcogen generates unwanted pieces of code ex: mibspi.
    Can we get more details on how to generate only required parts from halcogen ?
  • 0 in reply to sreenivasan m
    Genius 3705 points

    Also, in mibspi init, there is a while loop checking for buffer initialization to complete. Please provide us the maximum waiting time to consider.
    Also, in spnu499c.pdf, in SPIFMT register description for PARITYENA is not clearly documented. As per the document, for this field set to 0, parity is not enabled.

    But, it also says how parity operation works when this field is set to 0. Please confirm and update the document.

  • 0 in reply to sreenivasan m
    TI__Guru**** 197336 points
    Hello,

    The BUFINITACTIVE bit in MibSPI FLG register Indicates the status of multi-buffer initialization process. Software needs to poll for this bit to determine if it can proceed with the register configuration of multi-buffer mode registers or buffer handling.

    If the SPIFLG register is read while the multi-buffer RAM is being initialized, the BUFINITACTIVE bit will be read as 1. If SPIFLG is read after the internal automatic buffer initialization is complete, this bit will be read as 0.

    I don't know the clock cycles for buffer initialization.
  • 0 in reply to QJ Wang
    TI__Mastermind 49120 points

    Each MibSPIx on TMS570LS31x has 128 buffers. Initialization of these buffers takes 128 VCLK cycles for each MibSPIx module.

  • 0 in reply to QJ Wang
    TI__Guru**** 197336 points
    To increase fault detection of data transmission and reception, an odd or even parity bit can be added at the end of a data word. The parity generator can be enabled or disabled individually for each data format. If a received parity bit does not match with the locally calculated parity bit, the parity error flag (PARITYERR) is set and an interrupt is asserted (if enabled).

    When PARITYENA=0, a parity generator is enabled.

    The parity bit (1 bit) is transmitted following the data.
  • 0 in reply to QJ Wang
    Genius 3705 points
    Hi Wang,

    Can you please answer the question of infinite loop timeout in selftest as mentioned above.
    Also, for the above PARITYENA, documentation part is confusing doesn't give clarity on initialization 0 and 1. Can you recheck and update it.

    Also, in the code generated from halcogen, could see below comment (ex: in pinmux.c file)
    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */

    Can you please provide more information on what is SAFETYMCUSW 134S?

    Regards,
    M.Sreenivasan.
  • 0 in reply to sreenivasan m
    Genius 3705 points
    Hi Sunil/Wang,

    Can you please respond to the above queries posted?

    Regards,
    M.Sreenivasan.
  • 0 in reply to sreenivasan m
    TI__Guru**** 197336 points
    Regarding the parity bit in SPI:

    1 Enable/Disable parity for transmit and receive: PARITYENA in SPI data format register
    2. Parity polarity (odd or even parity bit): PARPOL in SPIFMT
    3. Parity error flag: PARITYERR in SPI Flag Register, and SPI Receive Buffer Register

    The parity bit will be transmitted on bit0 of the SIMO/SOMI lines. The receive parity is expected on bit0 of the SOMI/SIMO pins.