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Compiler/TMS570LS3137: Justification about J and DNM bit

Shivam Kakad
Expert 1355 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Tool/software: TI C/C++ Compiler

Hi,

I am using the TMS570LS3137 controller,

As per the ARM Cortex R4f document, we, as a software should not modify the DNM bits.

But the halcogen generated startup code includes(i.e. in _coreInitRegisters_ function),

mrs r1, cpsr
msr spsr_cxsf, r1

With this, We are writting all bit to 0, is there any justification why do we need to that?

and for the J bit,

though writing it as 1 we were not able to modify it.

Does it mean that we will be always reading that value as 0?

Is there anything required to enable that bit, for this TMS570LS3137 Porcessor?

Regards,

Shivam Kakad

 

  • 0
    TI__Guru** 116170 points

    Shivam,

    The comment on DNM applies only to CPSR not to SPSR as you can see here:

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Beidbjba.html

    the assembly code that you have shared there reads the CPSR and saves the context in SPSR so I do not see any violation of the spec. Also, please note that Halcogen is a helper tool to jump start development, so application developers need to review the auto generated to check compliance but I don`t see any issue with the code that you are highlighting.

    If you are looking for reference code for performing read modify write operation on CPSR, then you can refer to the code here:

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka3540.html

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Expert 1355 points

    But Here, as per the following instruction,

    msr spsr_cxsf, r1

    we are moving the content of r1 to the SPSR.

    But during the initialization function the R1 initialized to 0 only for 16 LSB which will get copied to SPSR.

    But the J and DNM bit are in the MSB's. but we are not initializing it.

    So is it as per the requirement?

    Can you please confirm the Same?

    Regards,

    Shivam Kakad 

  • 0 in reply to Shivam Kakad
    Expert 1355 points

    And also how are we initilazing the SPSR J bit?

    As reference manual tells that the msr instruction can not be used to write to the J bit.

    Regards,

    Shivam Kakad

  • 0
    TI__Mastermind 49120 points

    Shivam,

    mrs r1, cpsr
    msr spsr_cxsf, r1

    The above two instructions do not mean that we are writing zeros to SPSR. Please refer to the ARM instruction set manual for more details on the MRS and MSR instructions.

    The first instruction (MRS) reads from the current program status register (CPSR) into R1, and the next instruction copies this value in R1 into the Saved Program Status Register (SPSR) for the mode that the CPU is in. Both CPSR and SPSR have identical bit arrangements.

    Hope this helps.