TMS570LS3137: When cpu is run those function, what is cpu state? whether can run others

Hello,

The CPU is still in normal run state. Except for SL_selftest_SRAM(), other function can be interrupted. The contents of the SRAM before the test will be completely lost including content in the stack. User software must take care of data backup if required. Typically the PBIST tests are carried out at the beginning of application software.

Hello

Thank you 

 and SL_Selftest_Flash? is this function cpu  still normal run?

Hello

 where can i find those function,for example 

SL_SelfTest_SRAM

SL_SelfTest_FEE

SL_SelfTest_PSCON

SL_SelTest_EFuse

SL_SelTest_FLASH, when they are running,whether cpu can run interrupted function.where the papers,i can find

Hello,

Yes, CPU is in normal run state. When 2 bit ECC error is injected intentionally, the CPU will generate abort. The abort handler should clear the ESM state registers and branch back to the instruction after the one that caused the abort. Please refer to the example code generated by HALCoGen (dabort.asm)

CPU is able to handle the interrupt when doing selftest.

All the selftest APIs are located in sl_selftest.c

The user guide is in: C:\ti\Hercules\SafeTI Diagnostic Library\2.4.0\docs

OK!

 Thank you 

 I have two questions.

 1.as you said,that when SL_SelfTest_SRAM function is running,the cpu can't run interrupt function,but when  SL_Selftest_Flash is running,the cpu can run interrupt function. are they part of pbist？

2.The PBIST is usually run on device start-up as it is a destructive test,whether the pbist test is carried out ,cpu all can't run interrupt function.and

   Which tests is part of pbist ？

Best Regards

Hello Whong,

1. The CPU can't run interrupt when doing SRAM Pbist. But the CPU can handle the interrupt when doing SRAM selftest (ECC error injection). Flash selftest is not part of PBIST.

2. The PBIST is used to provide a very high diagnostic coverage on the implemented SRAMs at a transistor level, and has proven to be drastically more effective than software-based tests of SRAM. The PBIST tests are destructive to memory contents, and as such are typically run only at MCU initialization. However, you have the freedom to initiate the tests at any time when the CPU is operable. It is recommended to copy the data from the SRAM to be tested to a non-tested memory before test execution and to restore the data once the test is complete (for example MibSPI RAM). When test execution is complete, the SRAM can be utilized for normal operation. The remainder of device logic (for example the code in N2HET RAM) continues normal operation during SRAM test.

You can run the PBIST on one SRAM or on groups of SRAMs based on the execution time, which can be allocated to the PBIST diagnostic.