CCS/TMS570LC4357: Cache Enable/Disable

Hello,

1. After reset, cache is disabled by default. If cache has been enabled, use the following code example to disable the cache:

MRC p15, #0, R1, c1, c0, #0 ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<12 ; instruction cache disable
BIC R1, R1, #0x1 <<2 ; data cache disable
DSB
MCR p15, #0, R1, c1, c0, #0 ; disabled cache RAMs ISB

The _cacheDisable_() and _cacheEnable_() generated by HALCoGen can be used by your application. Those two functions are in HL_sys_core.asm.

2. Please use HALCoGen for MPU settings, and refer to ARM TRM regarding the MPU properties. 

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0460c/DDI0460C_cortexr5_trm.pdf

3. Both the instruction and data caches of theCPU are memory mapped in the device and can be accessed via the AXI-S slave port. Only the CPU core has point to point connection to the AXI-S slave port. DMA doesn't use cache.

Hello Waite,

The cache should be enabled.

You can use MPU to configure those two RAM regions to have different settings:

1. 448K region: cacheable. Use WriteBack mode for faster accesses, or WriteThrough mode if any of the other masters does a read to this memory.

2. 64K region: Non-cacheable