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CCS/LAUNCHXL2-TMS57012: After distributing flash for bootloader test I am not able to use Interrupt in Application code

Kalpesh Mhase
Intellectual 825 points
Part Number: LAUNCHXL2-TMS57012
Other Parts Discussed in Thread: TMS570LS1227, TMS570LS1224, HALCOGEN

Tool/software: Code Composer Studio

Hello,

I am currently working on developing CAN-based Bootloader for TMS570LS1224. Yes, there is a CAN-based Example but it is made for TMS570LS1227 MCU. So I preferred developing one by myself by referring to the example.

So now, I am using two different projects and  I am able to place these two codes with the different locations in Flash Memory by makes changes in a Linker cmd file(sys_link.cmd) and Interrupt vector file(sys_intvecs.asm). After debugging these projects I am able to make a jump from the first test Bootloader code to another test application code properly. 

Next thing I did is to use RTI based interrupt in Application code and re-debug the codes and test whether Bootloader code makes a proper jump to application code which is not happening.

The issue is that the bootloader program runs properly but after that, it does not jump to the Application code.

I have attached both the project please have a look.

I tried changing the interrupt vector file(sys_intvecs.asm) of Bootloader project parameters as given in bootloader CAN example.

The changes where done  from :

b _c_int00
undefEntry
b undefEntry
svcEntry
b svcEntry
prefetchEntry
b prefetchEntry
b _dabort
b phantomInterrupt
ldr pc,[pc,#-0x1b0]
ldr pc,[pc,#-0x1b0]

to

b _c_int00 ;0x00
b #0x1FFF8 ;0x04
b #0x1FFF8 ;0x08, Software interrupt
b #0x1FFF8 ;0x0C, Abort (prefetch)
b #0x1FFF8 ;0x10, Abort (data)
reservedEntry
b reservedEntry ;0x14
ldr pc,[pc, #-0x1b0] ;0x18
ldr pc,[pc, #-0x1b0] ;0x1C

where, 0x1FFF8 = Jump address (i.e. 0x20000) - 0x08

This causes the code to get into some error loop where ERR led on the lauchpad turns fulltime ON and program is not debuggable.

I think there might be some different changes in interrupt vector file (sys_intvecs.asm). But I am unable to get any documentation related to the interrupt vector file.

I tried reading following reference manual and documents:

1. spnu118u

2. Linker cmd file primer.

3. spnu515c

Please help me solve the issue and do give reference documentation which will help me edit interrupt vector file (sys_intvecs.asm).

8883.Projects.zip

  • 0
    TI__Guru**** 191666 points
    Hello,

    Please change the memory map in the cmd file of the application project. I just checked your code, your bootloader and application use a same cmd file and same interrupt vector table:

    1. Memory map defined in your cmd file of bootloader and application:
    MEMORY
    {
    VECTORS (X) : origin=0x00000000 length=0x00000020
    FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0
    STACKS (RW) : origin=0x08000000 length=0x00001500
    RAM (RW) : origin=0x08001500 length=0x0002EB00

    /* USER CODE BEGIN (2) */
    /* USER CODE END */
    }

    Please change change the starting address for VECTORS and FLASH0 for application (starting from 0x20000 in your example)

    2. Interrupt Vector table. Both projects use a same settings:

    ;resetEntry
    b _c_int00
    undefEntry
    b undefEntry
    svcEntry
    b svcEntry
    prefetchEntry
    b prefetchEntry
    b _dabort
    b phantomInterrupt
    ldr pc,[pc,#-0x1b0]
    ldr pc,[pc,#-0x1b0]

    If you comment out the jump instruction in bootloader code, can you get any error?
    If you program the application code to the beginning to the sector0 (use default cmd file), is there any error?
  • 0 in reply to QJ Wang
    Intellectual 825 points
    My apologies, the "Application Int" project got code generated via Halcogen and the changes which I made in Linker file & interrupt vector table where replaced by Halcogen generated code.
    You can observe clearly that Interrupt Vector table for both the projects do not use a same settings. The difference is
    In Application Project :
    resetEntry
    b _c_int00
    undefEntry
    b undefEntry
    svcEntry
    b svcEntry
    prefetchEntry
    b prefetchEntry
    b _dabort
    b phantomInterrupt
    ldr pc,[pc,#-0x1b0]
    ldr pc,[pc,#-0x1b0]

    In Bootloader Project:
    ;resetEntry
    b _c_int00
    undefEntry
    b undefEntry
    svcEntry
    b svcEntry
    prefetchEntry
    b prefetchEntry
    b _dabort
    b phantomInterrupt
    ldr pc,[pc,#-0x1b0]
    ldr pc,[pc,#-0x1b0]

    The change is resetEntry is not commented in Application Project.
  • 0 in reply to QJ Wang
    Intellectual 825 points

    I have got the interrupt based application code running properly. Also, the program is jumping from Bootloader to Interrupt based Application properly.

    This was resolved by changing the application linker file as per you recommended.

    I have attached edited projects please have a look.

    I also have another query which is as follows,

    The interrupt vector file which I am using for Bootloader is:

    ;resetEntry
          b _c_int00
          undefEntry
          b undefEntry
    svcEntry
          b svcEntry
    prefetchEntry
          b prefetchEntry
          b _dabort
          b phantomInterrupt
          ldr pc,[pc,#-0x1b0]
          ldr pc,[pc,#-0x1b0]

    And Can based bootloader Example is using: [Have also attached the can based example.]

          b _c_int00 ;0x00
          b #0x1FFF8 ;0x04
          b #0x1FFF8 ;0x08, Software interrupt
          b #0x1FFF8 ;0x0C, Abort (prefetch)
          b #0x1FFF8 ;0x10, Abort (data)
    reservedEntry
          b reservedEntry ;0x14
          ldr pc,[pc, #-0x1b0] ;0x18
          ldr pc,[pc, #-0x1b0] ;0x1C

    What is the difference? How can I understand what each line is doing?

    And also you haven't given any reference documentation which will help me edit interrupt vector file (sys_intvecs.asm).

    Please provide me with the same.

    2781.Edited Projects.rar

    6403.SafetyMCU_Bootloader.zip

  • 0 in reply to Kalpesh Mhase
    Intellectual 825 points
    Can anyone please help ?
  • 0 in reply to Kalpesh Mhase
    TI__Guru**** 191666 points
    Hello,

    The interrupt vector table has 8 entries in it. Each entry points to the corresponding interrupt service routine: for example the entry at address 0x08 points to the SW interrupt handler which is defined in bootloader and your application.

    When a SW interrupt occurs, the CPU will read the handler address at 0x08, then jump to 0x20008 which points to SW interrupt handler in application.
  • 0 in reply to QJ Wang
    Intellectual 825 points
    Which line represents "jump to 0x20008 which points to SW interrupt handler in application" is taking place.
    Then what does #0x1FFF8 represent and why it has to be [(application start addr) - 0x08].
    What does svcEntry, prefetchEntry, phantomInterrupt, _dabort represent, reservedEntry represents .
    And their are many such questions related to the file.

    So please provide me with some documentation related to the interrupt service routine file which will have all the details.
  • 0 in reply to Kalpesh Mhase
    TI__Guru**** 191666 points
    This is your exception vectors of bootloader:
    b _c_int00 ;0x00
    b #0x1FFF8 ;0x04
    b #0x1FFF8 ;0x08, Software interrupt
    b #0x1FFF8 ;0x0C, Abort (prefetch)
    b #0x1FFF8 ;0x10, Abort (data)
    reservedEntry
    b reservedEntry ;0x14
    ldr pc,[pc, #-0x1b0] ;0x18
    ldr pc,[pc, #-0x1b0] ;0x1C

    After the SW interrupt is received by the CPU, the CPU branches to 0x08. The ARM uses a pipeline in order to increase the speed of the flow of instructions to the processor. Rather than pointing to the instruction being executed, the PC points to the instruction being fetched. For ARM Cortex-R devics, Program Counter (PC) always pointers two instructions beyond the current executed instruction. In this case, PC equals to 0x08+0x08.

    b #0x1FFF8

    The offset for branch instructions (b or bl) is calculated by By taking the difference between the branch instruction and the target address minus 8 (to allow for the pipeline).
    offset=0x2008-0x08-0x08=0x1FFF8

    This is why I said It wil jump to 0x2008 to execute SW ISR in your application.

    ARM Cortex-R supports 7 exceptions:
    1. Reset offset from vector base is: 0x00
    2. Undefined Instruction offset from vector base is: 0x04
    3. Software Interrupt offset from vector base is: 0x08
    4. Prefetch Abort offset from vector base is: 0x0C
    5. Data Abort offset from vector base is: 0x10
    6. IRQ offset from vector base is: 0x18
    7. FIQ offset from vector base is: 0xIC

    Please refer to chapter 3 of ARM Cortex-R4 TRM for the details:
    infocenter.arm.com/.../DDI0363G_cortex_r4_r1p4_trm.pdf