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MSP430 USCI (SPI) timing issue

Other Parts Discussed in Thread: MSP430F5438A

Hi,

We are using MSP430F5438A SPI in master mode.
with some test, we found that both the Clock and the SIMO signal's
rising edges are almost the same.
We may have to delay the SIMO signal a little bit
in order to maintain the timing constraints for SPI mentioned in the datasheet.
if anybody experienced such timing issues with the MSP430F5438A SPI communication
please let us know if there is any suggestiongs.

Regards.

  • Kika said:
    with some test, we found that both the Clock and the SIMO signal's rising edges are almost the same.

    The UCCKPL and UCCKPH control bits of the USCI can be used to control the polarity and phase of clock w.r.t. the SIMO signal. See section 33.3.6.1 Serial Clock Polarity and Phase in the MSP430x5xx/MSP430x6xx Family User's Guide SLAU208J.

     Which SPI slave device are you interfacing to?

  • Hi,

    Thank you for the reply.

    I have tried changing the clock phase, but with no success.
    As both the clock and the SIMO signals have similar rising edges
    we are not able to have a proper SPI communication.
    The SPI slave is FRAM device.

    We tried the same with SPI bit banging using the GPIO
    and the communications works fine.
    The problem is with the hardware SPI.
    Is there any way to shift the SIMO signal(on the minus side)
    in order to maintain the timinig constraints required for the SPI communication.

    Regards.

  • Sorry.. solved the problem by changing the clock phase.

    Thank you for the help.

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