Own serial protocol

Hello,

2. Which interrupt signal will be used: from /SS or char received flag? Does msp247 will be able to storage and send this data through the UART, question is about bandwidth of SPI.

 Thank you in advance,

Mikołaj

I read their data sheet too.

I think it is easy to use their 8-bit digital mode. The F2xx SPI slave mode should be able to handle their EOC, D-Trig, and DO output signals. In addition to that, you need to supply them the CLK and ST input signals.

I do not know how to handle their 10-bit digital mode other than bit-banging, which is very slow.

Some F2xx may be able to handle their analog mode too.

Most Fxx can output SMCLK to one of the pins. If you have a SMCLK between 1MHz and 12MHz, this can be used for their CLK input.

At 12MHz, your SPI slave will need to handle 1 byte of incoming data each micro-second. This is very tough. But at 1MHz, you have 12 micro-second. Just make sure MCLK is fast enough!

Hello,

I will use 8-bit conversion. I know I have to read DO line, but when. Can I use interrupt from EOC (I think similar to /SS line) or D-Trig (as SPI clock).

I generated SCK for s10077 as you wrote, as SMCLK with div 8, from 16MHz crystal.

BR

Mikołaj

Hello,

I write code, using available example (msp430x24x_uscia0_spi_10.c - spi slave) but I don't see anything on my scope. I use echo function.

#include "msp430x24x.h"

volatile unsigned int i;

void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer

P5DIR |= 0x10; // P5.4= output direction
P5SEL |= 0x10; // P5.4= MCLK option select

P5DIR |= 0x20; // P5.5= output direction
P5SEL |= 0x20; // P5.5= SMCLK option select

BCSCTL1 &= ~XT2OFF; // Activate XT2 high freq xtal
BCSCTL3 |= XT2S_2; // 3 – 16MHz crystal or resonator

do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while (IFG1 & OFIFG); // OSCFault flag still set?

BCSCTL2 |= SELM_2 + DIVS_3 + SELS; // MCLK = XT2 HF XTAL (safe) + smclk div8

while (!(P3IN & 0x01)); // If clock sig from mstr stays low,
// it is not yet in SPI mode
P3SEL |= 0x31; // P3.0,4,5 USCI_A0 option select
UCA0CTL1 = UCSWRST; // **Put state machine in reset**
UCA0CTL0 |= UCCKPL + UCMSB + UCSYNC; // 3-pin, 8-bit SPI master
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
IE2 |= UCA0RXIE; // Enable USCI0 RX interrupt

for(;;){}
}

// Echo character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR (void)
{
while (!(IFG2 & UCA0TXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF; // only to see anything on scope
}

So, you did send a steady 2 MHz CLK. (The MSP430 is responsible to send CLK.) You should be able to see CLK on the scope.

Did you send a ST? It should be active low for at least 45 cycles of CLK. (The MSP430 is responsible to send ST.) You should be able to see ST on the scope too. 

30 some CLKs later, the 1D camera should send you D-Trig & DO in groups of 8 or 10. The camera also sends active low pulse to mark the end of each group of D-Trig & DO. Yes, you could use EOC for interrupt  There should be 1024 groups of D-Trig & DO and 1024 EOC for each ST. You should be able to see D-Trig, DO, and EOC on the scope.  (The 1D camera chip is responsible for sending all these three signals.)

Never mind sending echo and screw up your timing. Once you see that the 1D camera is sending D-Trig, DO, and EOC, it is up to the MSP430 SPI slave to receive and record them.

Hello,
I send a steady 2MHz clock wave to SCK pin of s10077 form SMCLK output (MCLK=16MHz div 8). I check it using scope.

ST line I connected to GND for a moment by hand, so it was more then 45cycles. Then I saw wave from DTrig, EOC and DO on my scope. But msp430 didn't generate interrupt, and did't send any data (echo loop).

s10077..............msp430
SCK<---------------SMCLK output
Dtrig------------->SCLK
EOC--------------->/SS
DO---------------->SIMO

If Vcc is 3.3V or above, you should set MCLK to 16 MHz.

You need to set up SPI to slave mode.

Enable interrupt for SPI data ready, or EOC edge.

Forget about sending echo.

Vcc is exacly 3.3V, what do you mean set MCLK to 16MHz. I connect XTCLK to X2 pins - crystal 16MHz.

BCSCTL1 &= ~XT2OFF; // Activate XT2 high freq xtal
BCSCTL3 |= XT2S_2; // 3 – 16MHz crystal or resonator

do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while (IFG1 & OFIFG); // OSCFault flag still set?

BCSCTL2 |= SELM_2 + DIVS_3 + SELS; // MCLK = XT2 HF XTAL (safe) + smclk div8

I set up SPI in slave mode:

while (!(P3IN & 0x01)); // If clock sig from mstr stays low,
// it is not yet in SPI mode
P3SEL |= 0x31; // P3.0,4,5 USCI_A0 option select
UCA0CTL1 = UCSWRST; // **Put state machine in reset**
UCA0CTL0 |= UCCKPL + UCMSB + UCSYNC; // 3-pin, 8-bit SPI slave
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**

And enable the Interrupt:

IE2 |= UCA0RXIE; // Enable USCI0 RX interrupt 

What I do wrong? 

Hello,

Could you tell me what can be wrong? I dont have any idea, what I need to change.

Thank you,

Mikołaj