Some background:
My application requires a very precise input capture. The high resolution timer on these MSP430F51x2 seemed ideal. I placed a very stable 10Mhz oscillator (0.28ppm) as the input oscillator and planned on multiplying it to 160MHz using TimerD's High Resolution Clock Generator in regulated mode. But it turned out (so far) not to work properly, because it seems to get multi-microsecond offsets from the reference clock (even though the "unlock" flag TDHUNLKIFG never gets set). I presume that this is due to the coarseness in the internal FLL controls. While measuring bypassing the High Resolution Generator gave readings that only differed by 1 count (at 10MHz), the 160MHz could have measuring differences of 500 or more, defeating the whole purpose of using higher frequency.
So it occurred to me that although the chip only supports up to 25 MHz on most other clock domains (MCLK, SMCLK, ACLK), perhaps I could provide the high frequency clock (e.g. 100 MHz) externally via TDCLK (more specifically, TD0CLK or TD1CLK). I could not find in the datasheet a maximum value for this port. Is it possible?